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target/arm: Factor out FWB=0 specific part of combine_cacheattrs()
Factor out the part of combine_cacheattrs() that is specific to handling HCR_EL2.FWB == 0. This is the part where we combine the memory type and cacheability attributes. The "force Outer Shareable for Device or Normal Inner-NC Outer-NC" logic remains in combine_cacheattrs() because it holds regardless (this is the equivalent of the pseudocode EffectiveShareability() function). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220505183950.2781801-3-peter.maydell@linaro.org
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@ -12578,6 +12578,46 @@ static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2)
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}
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}
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/*
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* Combine the memory type and cacheability attributes of
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* s1 and s2 for the HCR_EL2.FWB == 0 case, returning the
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* combined attributes in MAIR_EL1 format.
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*/
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static uint8_t combined_attrs_nofwb(CPUARMState *env,
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ARMCacheAttrs s1, ARMCacheAttrs s2)
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{
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uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs;
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s2_mair_attrs = convert_stage2_attrs(env, s2.attrs);
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s1lo = extract32(s1.attrs, 0, 4);
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s2lo = extract32(s2_mair_attrs, 0, 4);
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s1hi = extract32(s1.attrs, 4, 4);
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s2hi = extract32(s2_mair_attrs, 4, 4);
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/* Combine memory type and cacheability attributes */
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if (s1hi == 0 || s2hi == 0) {
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/* Device has precedence over normal */
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if (s1lo == 0 || s2lo == 0) {
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/* nGnRnE has precedence over anything */
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ret_attrs = 0;
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} else if (s1lo == 4 || s2lo == 4) {
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/* non-Reordering has precedence over Reordering */
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ret_attrs = 4; /* nGnRE */
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} else if (s1lo == 8 || s2lo == 8) {
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/* non-Gathering has precedence over Gathering */
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ret_attrs = 8; /* nGRE */
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} else {
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ret_attrs = 0xc; /* GRE */
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}
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} else { /* Normal memory */
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/* Outer/inner cacheability combine independently */
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ret_attrs = combine_cacheattr_nibble(s1hi, s2hi) << 4
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| combine_cacheattr_nibble(s1lo, s2lo);
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}
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return ret_attrs;
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}
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/* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
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* and CombineS1S2Desc()
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*
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@ -12588,26 +12628,17 @@ static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2)
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static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
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ARMCacheAttrs s1, ARMCacheAttrs s2)
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{
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uint8_t s1lo, s2lo, s1hi, s2hi;
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ARMCacheAttrs ret;
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bool tagged = false;
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uint8_t s2_mair_attrs;
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assert(s2.is_s2_format && !s1.is_s2_format);
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ret.is_s2_format = false;
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s2_mair_attrs = convert_stage2_attrs(env, s2.attrs);
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if (s1.attrs == 0xf0) {
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tagged = true;
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s1.attrs = 0xff;
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}
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s1lo = extract32(s1.attrs, 0, 4);
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s2lo = extract32(s2_mair_attrs, 0, 4);
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s1hi = extract32(s1.attrs, 4, 4);
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s2hi = extract32(s2_mair_attrs, 4, 4);
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/* Combine shareability attributes (table D4-43) */
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if (s1.shareability == 2 || s2.shareability == 2) {
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/* if either are outer-shareable, the result is outer-shareable */
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@ -12621,37 +12652,18 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
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}
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/* Combine memory type and cacheability attributes */
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if (s1hi == 0 || s2hi == 0) {
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/* Device has precedence over normal */
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if (s1lo == 0 || s2lo == 0) {
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/* nGnRnE has precedence over anything */
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ret.attrs = 0;
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} else if (s1lo == 4 || s2lo == 4) {
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/* non-Reordering has precedence over Reordering */
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ret.attrs = 4; /* nGnRE */
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} else if (s1lo == 8 || s2lo == 8) {
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/* non-Gathering has precedence over Gathering */
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ret.attrs = 8; /* nGRE */
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} else {
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ret.attrs = 0xc; /* GRE */
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}
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ret.attrs = combined_attrs_nofwb(env, s1, s2);
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/* Any location for which the resultant memory type is any
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* type of Device memory is always treated as Outer Shareable.
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*/
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/*
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* Any location for which the resultant memory type is any
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* type of Device memory is always treated as Outer Shareable.
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* Any location for which the resultant memory type is Normal
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* Inner Non-cacheable, Outer Non-cacheable is always treated
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* as Outer Shareable.
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* TODO: FEAT_XS adds another value (0x40) also meaning iNCoNC
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*/
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if ((ret.attrs & 0xf0) == 0 || ret.attrs == 0x44) {
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ret.shareability = 2;
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} else { /* Normal memory */
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/* Outer/inner cacheability combine independently */
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ret.attrs = combine_cacheattr_nibble(s1hi, s2hi) << 4
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| combine_cacheattr_nibble(s1lo, s2lo);
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if (ret.attrs == 0x44) {
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/* Any location for which the resultant memory type is Normal
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* Inner Non-cacheable, Outer Non-cacheable is always treated
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* as Outer Shareable.
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*/
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ret.shareability = 2;
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}
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}
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/* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */
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