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https://gitlab.com/qemu-project/qemu
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tcg-ppc64: Streamline qemu_ld/st insn selection
Using a table to look up insns of the right width and sign. Include support for the Power 2.06 LDBRX and STDBRX insns. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
28f2dba6dc
commit
49d9870a54
1 changed files with 56 additions and 110 deletions
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@ -44,6 +44,8 @@ static uint8_t *tb_ret_addr;
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#define GUEST_BASE 0
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#endif
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#define HAVE_ISA_2_06 0
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#ifdef CONFIG_USE_GUEST_BASE
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#define TCG_GUEST_BASE_REG 30
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#else
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@ -368,8 +370,10 @@ static int tcg_target_const_match (tcg_target_long val,
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#define CMPL XO31( 32)
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#define LHBRX XO31(790)
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#define LWBRX XO31(534)
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#define LDBRX XO31(532)
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#define STHBRX XO31(918)
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#define STWBRX XO31(662)
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#define STDBRX XO31(660)
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#define MFSPR XO31(339)
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#define MTSPR XO31(467)
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#define SRAWI XO31(824)
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@ -759,22 +763,44 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg r0, TCGReg r1, TCGReg r2,
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}
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#endif
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static const uint32_t qemu_ldx_opc[8] = {
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#ifdef TARGET_WORDS_BIGENDIAN
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LBZX, LHZX, LWZX, LDX,
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0, LHAX, LWAX, LDX
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#else
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LBZX, LHBRX, LWBRX, LDBRX,
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0, 0, 0, LDBRX,
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#endif
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};
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static const uint32_t qemu_stx_opc[4] = {
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#ifdef TARGET_WORDS_BIGENDIAN
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STBX, STHX, STWX, STDX
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#else
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STBX, STHBRX, STWBRX, STDBRX,
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#endif
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};
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static const uint32_t qemu_exts_opc[4] = {
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EXTSB, EXTSH, EXTSW, 0
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};
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static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
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{
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TCGReg addr_reg, data_reg, r0, r1, rbase;
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int bswap;
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uint32_t insn, s_bits;
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#ifdef CONFIG_SOFTMMU
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TCGReg r2, ir;
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int mem_index, s_bits;
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int mem_index;
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void *label1_ptr, *label2_ptr;
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#endif
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data_reg = *args++;
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addr_reg = *args++;
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s_bits = opc & 3;
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#ifdef CONFIG_SOFTMMU
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mem_index = *args;
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s_bits = opc & 3;
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r0 = 3;
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r1 = 4;
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@ -799,23 +825,11 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
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tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
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switch (opc) {
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case 0|4:
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tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
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break;
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case 1|4:
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tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
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break;
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case 2|4:
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tcg_out32 (s, EXTSW | RA (data_reg) | RS (3));
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break;
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case 0:
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case 1:
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case 2:
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case 3:
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if (data_reg != 3)
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tcg_out_mov (s, TCG_TYPE_I64, data_reg, 3);
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break;
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if (opc & 4) {
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insn = qemu_exts_opc[s_bits];
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tcg_out32(s, insn | RA(data_reg) | RS(3));
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} else if (data_reg != 3) {
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tcg_out_mov(s, TCG_TYPE_I64, data_reg, 3);
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}
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label2_ptr = s->code_ptr;
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tcg_out32 (s, B);
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@ -842,65 +856,19 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
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rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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bswap = 0;
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#else
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bswap = 1;
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#endif
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switch (opc) {
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default:
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case 0:
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tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
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break;
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case 0|4:
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tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
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tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
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break;
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case 1:
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if (bswap)
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tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
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else
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tcg_out32 (s, LHZX | TAB (data_reg, rbase, r0));
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break;
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case 1|4:
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if (bswap) {
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tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
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tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
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}
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else tcg_out32 (s, LHAX | TAB (data_reg, rbase, r0));
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break;
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case 2:
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if (bswap)
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tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
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else
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tcg_out32 (s, LWZX | TAB (data_reg, rbase, r0));
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break;
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case 2|4:
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if (bswap) {
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tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
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tcg_out32 (s, EXTSW | RA (data_reg) | RS (data_reg));
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}
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else tcg_out32 (s, LWAX | TAB (data_reg, rbase, r0));
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break;
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case 3:
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#ifdef CONFIG_USE_GUEST_BASE
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if (bswap) {
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tcg_out32(s, ADDI | TAI(r1, r0, 4));
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tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
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tcg_out32 (s, LWBRX | TAB ( r1, rbase, r1));
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tcg_out_rld (s, RLDIMI, data_reg, r1, 32, 0);
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}
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else tcg_out32 (s, LDX | TAB (data_reg, rbase, r0));
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#else
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if (bswap) {
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tcg_out_movi32 (s, 0, 4);
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tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
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tcg_out32 (s, LWBRX | RT ( r1) | RA (r0));
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tcg_out_rld (s, RLDIMI, data_reg, r1, 32, 0);
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}
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else tcg_out32 (s, LD | RT (data_reg) | RA (r0));
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#endif
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break;
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insn = qemu_ldx_opc[opc];
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if (!HAVE_ISA_2_06 && insn == LDBRX) {
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tcg_out32(s, ADDI | TAI(r1, r0, 4));
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tcg_out32(s, LWBRX | TAB(data_reg, rbase, r0));
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tcg_out32(s, LWBRX | TAB( r1, rbase, r1));
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tcg_out_rld(s, RLDIMI, data_reg, r1, 32, 0);
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} else if (insn) {
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tcg_out32(s, insn | TAB(data_reg, rbase, r0));
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} else {
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insn = qemu_ldx_opc[s_bits];
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tcg_out32(s, insn | TAB(data_reg, rbase, r0));
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insn = qemu_exts_opc[s_bits];
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tcg_out32 (s, insn | RA(data_reg) | RS(data_reg));
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}
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#ifdef CONFIG_SOFTMMU
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@ -911,7 +879,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
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static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
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{
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TCGReg addr_reg, r0, r1, rbase, data_reg;
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int bswap;
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uint32_t insn;
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#ifdef CONFIG_SOFTMMU
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TCGReg r2, ir;
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int mem_index;
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@ -975,36 +943,14 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
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rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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bswap = 0;
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#else
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bswap = 1;
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#endif
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switch (opc) {
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case 0:
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tcg_out32 (s, STBX | SAB (data_reg, rbase, r0));
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break;
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case 1:
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if (bswap)
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tcg_out32 (s, STHBRX | SAB (data_reg, rbase, r0));
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else
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tcg_out32 (s, STHX | SAB (data_reg, rbase, r0));
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break;
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case 2:
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if (bswap)
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tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
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else
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tcg_out32 (s, STWX | SAB (data_reg, rbase, r0));
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break;
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case 3:
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if (bswap) {
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tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
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tcg_out32(s, ADDI | TAI(r1, r0, 4));
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tcg_out_shri64(s, 0, data_reg, 32);
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tcg_out32 (s, STWBRX | SAB (0, rbase, r1));
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}
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else tcg_out32 (s, STDX | SAB (data_reg, rbase, r0));
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break;
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insn = qemu_stx_opc[opc];
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if (!HAVE_ISA_2_06 && insn == STDBRX) {
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tcg_out32(s, STWBRX | SAB(data_reg, rbase, r0));
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tcg_out32(s, ADDI | TAI(r1, r0, 4));
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tcg_out_shri64(s, 0, data_reg, 32);
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tcg_out32(s, STWBRX | SAB(0, rbase, r1));
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} else {
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tcg_out32(s, insn | SAB(data_reg, rbase, r0));
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}
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#ifdef CONFIG_SOFTMMU
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