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target/loongarch: Implement vabsd

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This patch includes:
- VABSD.{B/H/W/D}[U].

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-12-gaosong@loongson.cn>
This commit is contained in:
Song Gao 2023-05-04 20:27:37 +08:00
parent 39e9b0a741
commit 4972565967
No known key found for this signature in database
GPG key ID: 40A2FFF239263EDF
5 changed files with 133 additions and 0 deletions
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9
target/loongarch/disas.c
View file

@ -925,3 +925,12 @@ INSN_LSX(vavgr_bu, vvv)
INSN_LSX(vavgr_hu, vvv)
INSN_LSX(vavgr_wu, vvv)
INSN_LSX(vavgr_du, vvv)
INSN_LSX(vabsd_b, vvv)
INSN_LSX(vabsd_h, vvv)
INSN_LSX(vabsd_w, vvv)
INSN_LSX(vabsd_d, vvv)
INSN_LSX(vabsd_bu, vvv)
INSN_LSX(vabsd_hu, vvv)
INSN_LSX(vabsd_wu, vvv)
INSN_LSX(vabsd_du, vvv)

9
target/loongarch/helper.h
View file

@ -211,3 +211,12 @@ DEF_HELPER_FLAGS_4(vavgr_bu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vavgr_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vavgr_wu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vavgr_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vabsd_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vabsd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vabsd_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vabsd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vabsd_bu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vabsd_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vabsd_wu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vabsd_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

95
target/loongarch/insn_trans/trans_lsx.c.inc
View file

@ -1166,3 +1166,98 @@ TRANS(vavgr_bu, gvec_vvv, MO_8, do_vavgr_u)
TRANS(vavgr_hu, gvec_vvv, MO_16, do_vavgr_u)
TRANS(vavgr_wu, gvec_vvv, MO_32, do_vavgr_u)
TRANS(vavgr_du, gvec_vvv, MO_64, do_vavgr_u)
static void gen_vabsd_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
{
tcg_gen_smax_vec(vece, t, a, b);
tcg_gen_smin_vec(vece, a, a, b);
tcg_gen_sub_vec(vece, t, t, a);
}
static void do_vabsd_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz)
{
static const TCGOpcode vecop_list[] = {
INDEX_op_smax_vec, INDEX_op_smin_vec, INDEX_op_sub_vec, 0
};
static const GVecGen3 op[4] = {
{
.fniv = gen_vabsd_s,
.fno = gen_helper_vabsd_b,
.opt_opc = vecop_list,
.vece = MO_8
},
{
.fniv = gen_vabsd_s,
.fno = gen_helper_vabsd_h,
.opt_opc = vecop_list,
.vece = MO_16
},
{
.fniv = gen_vabsd_s,
.fno = gen_helper_vabsd_w,
.opt_opc = vecop_list,
.vece = MO_32
},
{
.fniv = gen_vabsd_s,
.fno = gen_helper_vabsd_d,
.opt_opc = vecop_list,
.vece = MO_64
},
};
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
}
static void gen_vabsd_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
{
tcg_gen_umax_vec(vece, t, a, b);
tcg_gen_umin_vec(vece, a, a, b);
tcg_gen_sub_vec(vece, t, t, a);
}
static void do_vabsd_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz)
{
static const TCGOpcode vecop_list[] = {
INDEX_op_umax_vec, INDEX_op_umin_vec, INDEX_op_sub_vec, 0
};
static const GVecGen3 op[4] = {
{
.fniv = gen_vabsd_u,
.fno = gen_helper_vabsd_bu,
.opt_opc = vecop_list,
.vece = MO_8
},
{
.fniv = gen_vabsd_u,
.fno = gen_helper_vabsd_hu,
.opt_opc = vecop_list,
.vece = MO_16
},
{
.fniv = gen_vabsd_u,
.fno = gen_helper_vabsd_wu,
.opt_opc = vecop_list,
.vece = MO_32
},
{
.fniv = gen_vabsd_u,
.fno = gen_helper_vabsd_du,
.opt_opc = vecop_list,
.vece = MO_64
},
};
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
}
TRANS(vabsd_b, gvec_vvv, MO_8, do_vabsd_s)
TRANS(vabsd_h, gvec_vvv, MO_16, do_vabsd_s)
TRANS(vabsd_w, gvec_vvv, MO_32, do_vabsd_s)
TRANS(vabsd_d, gvec_vvv, MO_64, do_vabsd_s)
TRANS(vabsd_bu, gvec_vvv, MO_8, do_vabsd_u)
TRANS(vabsd_hu, gvec_vvv, MO_16, do_vabsd_u)
TRANS(vabsd_wu, gvec_vvv, MO_32, do_vabsd_u)
TRANS(vabsd_du, gvec_vvv, MO_64, do_vabsd_u)

9
target/loongarch/insns.decode
View file

@ -619,3 +619,12 @@ vavgr_bu 0111 00000110 10100 ..... ..... ..... @vvv
vavgr_hu 0111 00000110 10101 ..... ..... ..... @vvv
vavgr_wu 0111 00000110 10110 ..... ..... ..... @vvv
vavgr_du 0111 00000110 10111 ..... ..... ..... @vvv
vabsd_b 0111 00000110 00000 ..... ..... ..... @vvv
vabsd_h 0111 00000110 00001 ..... ..... ..... @vvv
vabsd_w 0111 00000110 00010 ..... ..... ..... @vvv
vabsd_d 0111 00000110 00011 ..... ..... ..... @vvv
vabsd_bu 0111 00000110 00100 ..... ..... ..... @vvv
vabsd_hu 0111 00000110 00101 ..... ..... ..... @vvv
vabsd_wu 0111 00000110 00110 ..... ..... ..... @vvv
vabsd_du 0111 00000110 00111 ..... ..... ..... @vvv

11
target/loongarch/lsx_helper.c
View file

@ -307,3 +307,14 @@ DO_3OP(vavgr_bu, 8, UB, DO_VAVGR)
DO_3OP(vavgr_hu, 16, UH, DO_VAVGR)
DO_3OP(vavgr_wu, 32, UW, DO_VAVGR)
DO_3OP(vavgr_du, 64, UD, DO_VAVGR)
#define DO_VABSD(a, b) ((a > b) ? (a -b) : (b-a))
DO_3OP(vabsd_b, 8, B, DO_VABSD)
DO_3OP(vabsd_h, 16, H, DO_VABSD)
DO_3OP(vabsd_w, 32, W, DO_VABSD)
DO_3OP(vabsd_d, 64, D, DO_VABSD)
DO_3OP(vabsd_bu, 8, UB, DO_VABSD)
DO_3OP(vabsd_hu, 16, UH, DO_VABSD)
DO_3OP(vabsd_wu, 32, UW, DO_VABSD)
DO_3OP(vabsd_du, 64, UD, DO_VABSD)