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hw/arm/sbsa-ref: Simplify by moving the gic in the machine state
Make the gic a field in the machine state, and instead of filling an array of qemu_irq and passing it around, directly call qdev_get_gpio_in() on the gic field. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20191206162303.30338-1-philmd@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
Peter Maydell
parent
0d57b49992
commit
48ba18e6d3
1 changed files with 42 additions and 44 deletions
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@ -89,6 +89,7 @@ typedef struct {
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void *fdt;
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int fdt_size;
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int psci_conduit;
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DeviceState *gic;
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PFlashCFI01 *flash[2];
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} SBSAMachineState;
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@ -328,10 +329,9 @@ static void create_secure_ram(SBSAMachineState *sms,
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memory_region_add_subregion(secure_sysmem, base, secram);
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}
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static void create_gic(SBSAMachineState *sms, qemu_irq *pic)
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static void create_gic(SBSAMachineState *sms)
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{
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unsigned int smp_cpus = MACHINE(sms)->smp.cpus;
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DeviceState *gicdev;
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SysBusDevice *gicbusdev;
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const char *gictype;
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uint32_t redist0_capacity, redist0_count;
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@ -339,25 +339,25 @@ static void create_gic(SBSAMachineState *sms, qemu_irq *pic)
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gictype = gicv3_class_name();
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gicdev = qdev_create(NULL, gictype);
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qdev_prop_set_uint32(gicdev, "revision", 3);
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qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus);
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sms->gic = qdev_create(NULL, gictype);
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qdev_prop_set_uint32(sms->gic, "revision", 3);
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qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus);
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/*
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* Note that the num-irq property counts both internal and external
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* interrupts; there are always 32 of the former (mandated by GIC spec).
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*/
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qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32);
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qdev_prop_set_bit(gicdev, "has-security-extensions", true);
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qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32);
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qdev_prop_set_bit(sms->gic, "has-security-extensions", true);
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redist0_capacity =
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sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE;
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redist0_count = MIN(smp_cpus, redist0_capacity);
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qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1);
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qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count);
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qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1);
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qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count);
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qdev_init_nofail(gicdev);
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gicbusdev = SYS_BUS_DEVICE(gicdev);
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qdev_init_nofail(sms->gic);
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gicbusdev = SYS_BUS_DEVICE(sms->gic);
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sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
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sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base);
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@ -383,15 +383,15 @@ static void create_gic(SBSAMachineState *sms, qemu_irq *pic)
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for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
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qdev_connect_gpio_out(cpudev, irq,
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qdev_get_gpio_in(gicdev,
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qdev_get_gpio_in(sms->gic,
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ppibase + timer_irq[irq]));
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}
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qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
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qdev_get_gpio_in(gicdev, ppibase
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qdev_get_gpio_in(sms->gic, ppibase
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+ ARCH_GIC_MAINT_IRQ));
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qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
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qdev_get_gpio_in(gicdev, ppibase
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qdev_get_gpio_in(sms->gic, ppibase
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+ VIRTUAL_PMU_IRQ));
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sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
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@ -402,13 +402,9 @@ static void create_gic(SBSAMachineState *sms, qemu_irq *pic)
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sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
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qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
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}
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for (i = 0; i < NUM_IRQS; i++) {
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pic[i] = qdev_get_gpio_in(gicdev, i);
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}
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}
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static void create_uart(const SBSAMachineState *sms, qemu_irq *pic, int uart,
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static void create_uart(const SBSAMachineState *sms, int uart,
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MemoryRegion *mem, Chardev *chr)
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{
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hwaddr base = sbsa_ref_memmap[uart].base;
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@ -420,15 +416,15 @@ static void create_uart(const SBSAMachineState *sms, qemu_irq *pic, int uart,
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qdev_init_nofail(dev);
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memory_region_add_subregion(mem, base,
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sysbus_mmio_get_region(s, 0));
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sysbus_connect_irq(s, 0, pic[irq]);
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sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq));
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}
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static void create_rtc(const SBSAMachineState *sms, qemu_irq *pic)
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static void create_rtc(const SBSAMachineState *sms)
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{
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hwaddr base = sbsa_ref_memmap[SBSA_RTC].base;
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int irq = sbsa_ref_irqmap[SBSA_RTC];
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sysbus_create_simple("pl031", base, pic[irq]);
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sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq));
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}
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static DeviceState *gpio_key_dev;
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@ -442,13 +438,14 @@ static Notifier sbsa_ref_powerdown_notifier = {
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.notify = sbsa_ref_powerdown_req
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};
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static void create_gpio(const SBSAMachineState *sms, qemu_irq *pic)
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static void create_gpio(const SBSAMachineState *sms)
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{
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DeviceState *pl061_dev;
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hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base;
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int irq = sbsa_ref_irqmap[SBSA_GPIO];
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pl061_dev = sysbus_create_simple("pl061", base, pic[irq]);
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pl061_dev = sysbus_create_simple("pl061", base,
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qdev_get_gpio_in(sms->gic, irq));
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gpio_key_dev = sysbus_create_simple("gpio-key", -1,
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qdev_get_gpio_in(pl061_dev, 3));
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@ -457,7 +454,7 @@ static void create_gpio(const SBSAMachineState *sms, qemu_irq *pic)
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qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier);
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}
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static void create_ahci(const SBSAMachineState *sms, qemu_irq *pic)
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static void create_ahci(const SBSAMachineState *sms)
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{
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hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base;
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int irq = sbsa_ref_irqmap[SBSA_AHCI];
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@ -471,7 +468,7 @@ static void create_ahci(const SBSAMachineState *sms, qemu_irq *pic)
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qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS);
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qdev_init_nofail(dev);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irq]);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq));
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sysahci = SYSBUS_AHCI(dev);
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ahci = &sysahci->ahci;
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@ -484,16 +481,16 @@ static void create_ahci(const SBSAMachineState *sms, qemu_irq *pic)
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}
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}
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static void create_ehci(const SBSAMachineState *sms, qemu_irq *pic)
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static void create_ehci(const SBSAMachineState *sms)
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{
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hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base;
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int irq = sbsa_ref_irqmap[SBSA_EHCI];
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sysbus_create_simple("platform-ehci-usb", base, pic[irq]);
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sysbus_create_simple("platform-ehci-usb", base,
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qdev_get_gpio_in(sms->gic, irq));
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}
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static void create_smmu(const SBSAMachineState *sms, qemu_irq *pic,
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PCIBus *bus)
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static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
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{
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hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base;
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int irq = sbsa_ref_irqmap[SBSA_SMMU];
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@ -507,11 +504,12 @@ static void create_smmu(const SBSAMachineState *sms, qemu_irq *pic,
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qdev_init_nofail(dev);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
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for (i = 0; i < NUM_SMMU_IRQS; i++) {
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
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qdev_get_gpio_in(sms->gic, irq + 1));
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}
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}
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static void create_pcie(SBSAMachineState *sms, qemu_irq *pic)
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static void create_pcie(SBSAMachineState *sms)
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{
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hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base;
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hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size;
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@ -555,7 +553,8 @@ static void create_pcie(SBSAMachineState *sms, qemu_irq *pic)
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
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for (i = 0; i < GPEX_NUM_IRQS; i++) {
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
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qdev_get_gpio_in(sms->gic, irq + 1));
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gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
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}
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@ -574,7 +573,7 @@ static void create_pcie(SBSAMachineState *sms, qemu_irq *pic)
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pci_create_simple(pci->bus, -1, "VGA");
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create_smmu(sms, pic, pci->bus);
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create_smmu(sms, pci->bus);
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}
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static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size)
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@ -598,7 +597,6 @@ static void sbsa_ref_init(MachineState *machine)
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bool firmware_loaded;
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const CPUArchIdList *possible_cpus;
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int n, sbsa_max_cpus;
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qemu_irq pic[NUM_IRQS];
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if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) {
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error_report("sbsa-ref: CPU type other than the built-in "
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@ -695,22 +693,22 @@ static void sbsa_ref_init(MachineState *machine)
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create_secure_ram(sms, secure_sysmem);
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create_gic(sms, pic);
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create_gic(sms);
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create_uart(sms, pic, SBSA_UART, sysmem, serial_hd(0));
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create_uart(sms, pic, SBSA_SECURE_UART, secure_sysmem, serial_hd(1));
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create_uart(sms, SBSA_UART, sysmem, serial_hd(0));
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create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1));
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/* Second secure UART for RAS and MM from EL0 */
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create_uart(sms, pic, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2));
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create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2));
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create_rtc(sms, pic);
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create_rtc(sms);
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create_gpio(sms, pic);
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create_gpio(sms);
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create_ahci(sms, pic);
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create_ahci(sms);
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create_ehci(sms, pic);
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create_ehci(sms);
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create_pcie(sms, pic);
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create_pcie(sms);
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sms->bootinfo.ram_size = machine->ram_size;
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sms->bootinfo.nb_cpus = smp_cpus;
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