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disas: arm: QOMify target specific disas setup
Move the target_disas() ARM specifics to the QOM disas_set_info hook and delete the ARM specific code in disas.c. This has the extra advantage of the more fully featured target_disas() implementation now applying to monitor_disas(). Currently, target_disas() has multi-endian, thumb and AArch64 support whereas the existing monitor_disas() support only has vanilla AA32 support. E.G. Running an AA64 linux kernel the following -d in_asm disas happens (taget_disas()): IN: 0x0000000040000000: 580000c0 ldr x0, pc+24 (addr 0x40000018) 0x0000000040000004: aa1f03e1 mov x1, xzr However before this patch, disasing the same from the monitor: (qemu) xp/i 0x40000000 0x0000000040000000: 580000c0 stmdapl r0, {r6, r7} After this patch: (qemu) xp/i 0x40000000 0x0000000040000000: 580000c0 ldr x0, pc+24 (addr 0x40000018) Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
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32
disas.c
32
disas.c
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@ -151,14 +151,6 @@ bfd_vma bfd_getb16 (const bfd_byte *addr)
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return (bfd_vma) v;
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}
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#ifdef TARGET_ARM
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static int
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print_insn_thumb1(bfd_vma pc, disassemble_info *info)
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{
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return print_insn_arm(pc | 1, info);
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}
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#endif
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static int print_insn_objdump(bfd_vma pc, disassemble_info *info,
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const char *prefix)
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{
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@ -191,7 +183,6 @@ static int print_insn_od_target(bfd_vma pc, disassemble_info *info)
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/* Disassemble this for me please... (debugging). 'flags' has the following
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values:
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i386 - 1 means 16 bit code, 2 means 64 bit code
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arm - bit 0 = thumb, bit 1 = reverse endian, bit 2 = A64
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ppc - bits 0:15 specify (optionally) the machine instruction set;
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bit 16 indicates little endian.
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other targets - unused
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@ -231,27 +222,6 @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,
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s.info.mach = bfd_mach_i386_i386;
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}
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s.info.print_insn = print_insn_i386;
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#elif defined(TARGET_ARM)
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if (flags & 4) {
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/* We might not be compiled with the A64 disassembler
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* because it needs a C++ compiler; in that case we will
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* fall through to the default print_insn_od case.
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*/
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#if defined(CONFIG_ARM_A64_DIS)
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s.info.print_insn = print_insn_arm_a64;
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#endif
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} else if (flags & 1) {
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s.info.print_insn = print_insn_thumb1;
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} else {
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s.info.print_insn = print_insn_arm;
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}
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if (flags & 2) {
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#ifdef TARGET_WORDS_BIGENDIAN
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s.info.endian = BFD_ENDIAN_LITTLE;
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#else
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s.info.endian = BFD_ENDIAN_BIG;
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#endif
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}
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#elif defined(TARGET_SPARC)
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s.info.print_insn = print_insn_sparc;
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#ifdef TARGET_SPARC64
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@ -488,8 +458,6 @@ void monitor_disas(Monitor *mon, CPUState *cpu,
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s.info.mach = bfd_mach_i386_i386;
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}
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s.info.print_insn = print_insn_i386;
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#elif defined(TARGET_ARM)
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s.info.print_insn = print_insn_arm;
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#elif defined(TARGET_ALPHA)
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s.info.print_insn = print_insn_alpha;
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#elif defined(TARGET_SPARC)
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@ -382,6 +382,39 @@ static inline void unset_feature(CPUARMState *env, int feature)
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env->features &= ~(1ULL << feature);
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}
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static int
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print_insn_thumb1(bfd_vma pc, disassemble_info *info)
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{
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return print_insn_arm(pc | 1, info);
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}
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static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
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{
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ARMCPU *ac = ARM_CPU(cpu);
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CPUARMState *env = &ac->env;
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if (is_a64(env)) {
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/* We might not be compiled with the A64 disassembler
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* because it needs a C++ compiler. Leave print_insn
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* unset in this case to use the caller default behaviour.
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*/
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#if defined(CONFIG_ARM_A64_DIS)
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info->print_insn = print_insn_arm_a64;
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#endif
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} else if (env->thumb) {
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info->print_insn = print_insn_thumb1;
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} else {
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info->print_insn = print_insn_arm;
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}
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if (env->bswap_code) {
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#ifdef TARGET_WORDS_BIGENDIAN
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info->endian = BFD_ENDIAN_LITTLE;
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#else
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info->endian = BFD_ENDIAN_BIG;
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#endif
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}
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}
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#define ARM_CPUS_PER_CLUSTER 8
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static void arm_cpu_initfn(Object *obj)
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@ -1368,6 +1401,8 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
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cc->gdb_core_xml_file = "arm-core.xml";
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cc->gdb_stop_before_watchpoint = true;
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cc->debug_excp_handler = arm_debug_excp_handler;
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cc->disas_set_info = arm_disas_set_info;
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}
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static void cpu_register(const ARMCPUInfo *info)
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