mirror of
https://gitlab.com/qemu-project/qemu
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target-xtensa: add dc232b core and board
This is Diamond 232L Standard Core Rev.B (LE). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Max Filippov
Blue Swirl
parent
4dd85b6b63
commit
47d05a8629
4 changed files with 546 additions and 0 deletions
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@ -370,6 +370,7 @@ obj-alpha-y += vga.o cirrus_vga.o
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obj-xtensa-y += xtensa_pic.o
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obj-xtensa-y += xtensa_sample.o
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obj-xtensa-y += xtensa_dc232b.o
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obj-xtensa-y += xtensa-semi.o
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main.o: QEMU_CFLAGS+=$(GPROF_CFLAGS)
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116
hw/xtensa_dc232b.c
Normal file
116
hw/xtensa_dc232b.c
Normal file
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@ -0,0 +1,116 @@
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/*
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* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "sysemu.h"
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#include "boards.h"
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#include "loader.h"
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#include "elf.h"
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#include "memory.h"
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#include "exec-memory.h"
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static uint64_t translate_phys_addr(void *env, uint64_t addr)
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{
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return cpu_get_phys_page_debug(env, addr);
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}
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static void dc232b_reset(void *env)
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{
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cpu_reset(env);
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}
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static void dc232b_init(ram_addr_t ram_size,
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const char *boot_device,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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CPUState *env = NULL;
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MemoryRegion *ram, *rom;
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int n;
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for (n = 0; n < smp_cpus; n++) {
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env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "Unable to find CPU definition\n");
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exit(1);
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}
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env->sregs[PRID] = n;
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qemu_register_reset(dc232b_reset, env);
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/* Need MMU initialized prior to ELF loading,
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* so that ELF gets loaded into virtual addresses
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*/
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dc232b_reset(env);
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}
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ram = g_malloc(sizeof(*ram));
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memory_region_init_ram(ram, NULL, "xtensa.sram", ram_size);
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memory_region_add_subregion(get_system_memory(), 0, ram);
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rom = g_malloc(sizeof(*rom));
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memory_region_init_ram(rom, NULL, "xtensa.rom", 0x1000);
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memory_region_add_subregion(get_system_memory(), 0xfe000000, rom);
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if (kernel_filename) {
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uint64_t elf_entry;
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uint64_t elf_lowaddr;
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#ifdef TARGET_WORDS_BIGENDIAN
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int success = load_elf(kernel_filename, translate_phys_addr, env,
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&elf_entry, &elf_lowaddr, NULL, 1, ELF_MACHINE, 0);
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#else
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int success = load_elf(kernel_filename, translate_phys_addr, env,
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&elf_entry, &elf_lowaddr, NULL, 0, ELF_MACHINE, 0);
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#endif
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if (success > 0) {
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env->pc = elf_entry;
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}
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}
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}
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static void xtensa_dc232b_init(ram_addr_t ram_size,
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const char *boot_device,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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if (!cpu_model) {
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cpu_model = "dc232b";
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}
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dc232b_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
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initrd_filename, cpu_model);
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}
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static QEMUMachine xtensa_dc232b_machine = {
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.name = "dc232b",
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.desc = "Diamond 232L Standard Core Rev.B (LE) (dc232b)",
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.init = xtensa_dc232b_init,
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.max_cpus = 4,
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};
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static void xtensa_dc232b_machine_init(void)
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{
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qemu_register_machine(&xtensa_dc232b_machine);
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}
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machine_init(xtensa_dc232b_machine_init);
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261
target-xtensa/gdb-config-dc232b.c
Normal file
261
target-xtensa/gdb-config-dc232b.c
Normal file
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@ -0,0 +1,261 @@
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/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
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Copyright (C) 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor,
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Boston, MA 02110-1301, USA. */
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XTREG(0, 0, 32, 4, 4, 0x0020, 0x0006, -2, 9, 0x0100, pc,
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0, 0, 0, 0, 0, 0)
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XTREG(1, 4, 32, 4, 4, 0x0100, 0x0006, -2, 1, 0x0002, ar0,
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0, 0, 0, 0, 0, 0)
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XTREG(2, 8, 32, 4, 4, 0x0101, 0x0006, -2, 1, 0x0002, ar1,
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0, 0, 0, 0, 0, 0)
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XTREG(3, 12, 32, 4, 4, 0x0102, 0x0006, -2, 1, 0x0002, ar2,
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0, 0, 0, 0, 0, 0)
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XTREG(4, 16, 32, 4, 4, 0x0103, 0x0006, -2, 1, 0x0002, ar3,
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0, 0, 0, 0, 0, 0)
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XTREG(5, 20, 32, 4, 4, 0x0104, 0x0006, -2, 1, 0x0002, ar4,
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0, 0, 0, 0, 0, 0)
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XTREG(6, 24, 32, 4, 4, 0x0105, 0x0006, -2, 1, 0x0002, ar5,
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0, 0, 0, 0, 0, 0)
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XTREG(7, 28, 32, 4, 4, 0x0106, 0x0006, -2, 1, 0x0002, ar6,
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0, 0, 0, 0, 0, 0)
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XTREG(8, 32, 32, 4, 4, 0x0107, 0x0006, -2, 1, 0x0002, ar7,
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0, 0, 0, 0, 0, 0)
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XTREG(9, 36, 32, 4, 4, 0x0108, 0x0006, -2, 1, 0x0002, ar8,
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0, 0, 0, 0, 0, 0)
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XTREG(10, 40, 32, 4, 4, 0x0109, 0x0006, -2, 1, 0x0002, ar9,
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0, 0, 0, 0, 0, 0)
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XTREG(11, 44, 32, 4, 4, 0x010a, 0x0006, -2, 1, 0x0002, ar10,
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0, 0, 0, 0, 0, 0)
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XTREG(12, 48, 32, 4, 4, 0x010b, 0x0006, -2, 1, 0x0002, ar11,
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0, 0, 0, 0, 0, 0)
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XTREG(13, 52, 32, 4, 4, 0x010c, 0x0006, -2, 1, 0x0002, ar12,
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0, 0, 0, 0, 0, 0)
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XTREG(14, 56, 32, 4, 4, 0x010d, 0x0006, -2, 1, 0x0002, ar13,
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0, 0, 0, 0, 0, 0)
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XTREG(15, 60, 32, 4, 4, 0x010e, 0x0006, -2, 1, 0x0002, ar14,
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0, 0, 0, 0, 0, 0)
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XTREG(16, 64, 32, 4, 4, 0x010f, 0x0006, -2, 1, 0x0002, ar15,
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0, 0, 0, 0, 0, 0)
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XTREG(17, 68, 32, 4, 4, 0x0110, 0x0006, -2, 1, 0x0002, ar16,
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0, 0, 0, 0, 0, 0)
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XTREG(18, 72, 32, 4, 4, 0x0111, 0x0006, -2, 1, 0x0002, ar17,
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0, 0, 0, 0, 0, 0)
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XTREG(19, 76, 32, 4, 4, 0x0112, 0x0006, -2, 1, 0x0002, ar18,
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0, 0, 0, 0, 0, 0)
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XTREG(20, 80, 32, 4, 4, 0x0113, 0x0006, -2, 1, 0x0002, ar19,
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0, 0, 0, 0, 0, 0)
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XTREG(21, 84, 32, 4, 4, 0x0114, 0x0006, -2, 1, 0x0002, ar20,
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0, 0, 0, 0, 0, 0)
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XTREG(22, 88, 32, 4, 4, 0x0115, 0x0006, -2, 1, 0x0002, ar21,
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0, 0, 0, 0, 0, 0)
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XTREG(23, 92, 32, 4, 4, 0x0116, 0x0006, -2, 1, 0x0002, ar22,
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0, 0, 0, 0, 0, 0)
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XTREG(24, 96, 32, 4, 4, 0x0117, 0x0006, -2, 1, 0x0002, ar23,
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0, 0, 0, 0, 0, 0)
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XTREG(25, 100, 32, 4, 4, 0x0118, 0x0006, -2, 1, 0x0002, ar24,
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0, 0, 0, 0, 0, 0)
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XTREG(26, 104, 32, 4, 4, 0x0119, 0x0006, -2, 1, 0x0002, ar25,
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0, 0, 0, 0, 0, 0)
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XTREG(27, 108, 32, 4, 4, 0x011a, 0x0006, -2, 1, 0x0002, ar26,
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0, 0, 0, 0, 0, 0)
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XTREG(28, 112, 32, 4, 4, 0x011b, 0x0006, -2, 1, 0x0002, ar27,
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0, 0, 0, 0, 0, 0)
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XTREG(29, 116, 32, 4, 4, 0x011c, 0x0006, -2, 1, 0x0002, ar28,
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0, 0, 0, 0, 0, 0)
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XTREG(30, 120, 32, 4, 4, 0x011d, 0x0006, -2, 1, 0x0002, ar29,
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0, 0, 0, 0, 0, 0)
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XTREG(31, 124, 32, 4, 4, 0x011e, 0x0006, -2, 1, 0x0002, ar30,
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0, 0, 0, 0, 0, 0)
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XTREG(32, 128, 32, 4, 4, 0x011f, 0x0006, -2, 1, 0x0002, ar31,
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0, 0, 0, 0, 0, 0)
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XTREG(33, 132, 32, 4, 4, 0x0200, 0x0006, -2, 2, 0x1100, lbeg,
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0, 0, 0, 0, 0, 0)
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XTREG(34, 136, 32, 4, 4, 0x0201, 0x0006, -2, 2, 0x1100, lend,
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0, 0, 0, 0, 0, 0)
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XTREG(35, 140, 32, 4, 4, 0x0202, 0x0006, -2, 2, 0x1100, lcount,
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0, 0, 0, 0, 0, 0)
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XTREG(36, 144, 6, 4, 4, 0x0203, 0x0006, -2, 2, 0x1100, sar,
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0, 0, 0, 0, 0, 0)
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XTREG(37, 148, 32, 4, 4, 0x0205, 0x0006, -2, 2, 0x1100, litbase,
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0, 0, 0, 0, 0, 0)
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XTREG(38, 152, 3, 4, 4, 0x0248, 0x0006, -2, 2, 0x1002, windowbase,
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0, 0, 0, 0, 0, 0)
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XTREG(39, 156, 8, 4, 4, 0x0249, 0x0006, -2, 2, 0x1002, windowstart,
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0, 0, 0, 0, 0, 0)
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XTREG(40, 160, 32, 4, 4, 0x02b0, 0x0002, -2, 2, 0x1000, sr176,
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0, 0, 0, 0, 0, 0)
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XTREG(41, 164, 32, 4, 4, 0x02d0, 0x0002, -2, 2, 0x1000, sr208,
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0, 0, 0, 0, 0, 0)
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XTREG(42, 168, 19, 4, 4, 0x02e6, 0x0006, -2, 2, 0x1100, ps,
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0, 0, 0, 0, 0, 0)
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XTREG(43, 172, 32, 4, 4, 0x03e7, 0x0006, -2, 3, 0x0110, threadptr,
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0, 0, 0, 0, 0, 0)
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XTREG(44, 176, 32, 4, 4, 0x020c, 0x0006, -1, 2, 0x1100, scompare1,
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0, 0, 0, 0, 0, 0)
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XTREG(45, 180, 32, 4, 4, 0x0210, 0x0006, -1, 2, 0x1100, acclo,
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0, 0, 0, 0, 0, 0)
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XTREG(46, 184, 8, 4, 4, 0x0211, 0x0006, -1, 2, 0x1100, acchi,
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0, 0, 0, 0, 0, 0)
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XTREG(47, 188, 32, 4, 4, 0x0220, 0x0006, -1, 2, 0x1100, m0,
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0, 0, 0, 0, 0, 0)
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XTREG(48, 192, 32, 4, 4, 0x0221, 0x0006, -1, 2, 0x1100, m1,
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0, 0, 0, 0, 0, 0)
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XTREG(49, 196, 32, 4, 4, 0x0222, 0x0006, -1, 2, 0x1100, m2,
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0, 0, 0, 0, 0, 0)
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XTREG(50, 200, 32, 4, 4, 0x0223, 0x0006, -1, 2, 0x1100, m3,
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0, 0, 0, 0, 0, 0)
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XTREG(51, 204, 32, 4, 4, 0x03e6, 0x000e, -1, 3, 0x0110, expstate,
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0, 0, 0, 0, 0, 0)
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XTREG(52, 208, 32, 4, 4, 0x0253, 0x0007, -2, 2, 0x1000, ptevaddr,
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0, 0, 0, 0, 0, 0)
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XTREG(53, 212, 32, 4, 4, 0x0259, 0x000d, -2, 2, 0x1000, mmid,
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0, 0, 0, 0, 0, 0)
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XTREG(54, 216, 32, 4, 4, 0x025a, 0x0007, -2, 2, 0x1000, rasid,
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0, 0, 0, 0, 0, 0)
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XTREG(55, 220, 18, 4, 4, 0x025b, 0x0007, -2, 2, 0x1000, itlbcfg,
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0, 0, 0, 0, 0, 0)
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XTREG(56, 224, 18, 4, 4, 0x025c, 0x0007, -2, 2, 0x1000, dtlbcfg,
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0, 0, 0, 0, 0, 0)
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XTREG(57, 228, 2, 4, 4, 0x0260, 0x0007, -2, 2, 0x1000, ibreakenable,
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0, 0, 0, 0, 0, 0)
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XTREG(58, 232, 32, 4, 4, 0x0268, 0x0007, -2, 2, 0x1000, ddr,
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0, 0, 0, 0, 0, 0)
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XTREG(59, 236, 32, 4, 4, 0x0280, 0x0007, -2, 2, 0x1000, ibreaka0,
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0, 0, 0, 0, 0, 0)
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XTREG(60, 240, 32, 4, 4, 0x0281, 0x0007, -2, 2, 0x1000, ibreaka1,
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0, 0, 0, 0, 0, 0)
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XTREG(61, 244, 32, 4, 4, 0x0290, 0x0007, -2, 2, 0x1000, dbreaka0,
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0, 0, 0, 0, 0, 0)
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XTREG(62, 248, 32, 4, 4, 0x0291, 0x0007, -2, 2, 0x1000, dbreaka1,
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0, 0, 0, 0, 0, 0)
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XTREG(63, 252, 32, 4, 4, 0x02a0, 0x0007, -2, 2, 0x1000, dbreakc0,
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0, 0, 0, 0, 0, 0)
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XTREG(64, 256, 32, 4, 4, 0x02a1, 0x0007, -2, 2, 0x1000, dbreakc1,
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0, 0, 0, 0, 0, 0)
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XTREG(65, 260, 32, 4, 4, 0x02b1, 0x0007, -2, 2, 0x1000, epc1,
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0, 0, 0, 0, 0, 0)
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XTREG(66, 264, 32, 4, 4, 0x02b2, 0x0007, -2, 2, 0x1000, epc2,
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0, 0, 0, 0, 0, 0)
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XTREG(67, 268, 32, 4, 4, 0x02b3, 0x0007, -2, 2, 0x1000, epc3,
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0, 0, 0, 0, 0, 0)
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XTREG(68, 272, 32, 4, 4, 0x02b4, 0x0007, -2, 2, 0x1000, epc4,
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0, 0, 0, 0, 0, 0)
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XTREG(69, 276, 32, 4, 4, 0x02b5, 0x0007, -2, 2, 0x1000, epc5,
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0, 0, 0, 0, 0, 0)
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XTREG(70, 280, 32, 4, 4, 0x02b6, 0x0007, -2, 2, 0x1000, epc6,
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0, 0, 0, 0, 0, 0)
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XTREG(71, 284, 32, 4, 4, 0x02b7, 0x0007, -2, 2, 0x1000, epc7,
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0, 0, 0, 0, 0, 0)
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XTREG(72, 288, 32, 4, 4, 0x02c0, 0x0007, -2, 2, 0x1000, depc,
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0, 0, 0, 0, 0, 0)
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XTREG(73, 292, 19, 4, 4, 0x02c2, 0x0007, -2, 2, 0x1000, eps2,
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0, 0, 0, 0, 0, 0)
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XTREG(74, 296, 19, 4, 4, 0x02c3, 0x0007, -2, 2, 0x1000, eps3,
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0, 0, 0, 0, 0, 0)
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XTREG(75, 300, 19, 4, 4, 0x02c4, 0x0007, -2, 2, 0x1000, eps4,
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0, 0, 0, 0, 0, 0)
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XTREG(76, 304, 19, 4, 4, 0x02c5, 0x0007, -2, 2, 0x1000, eps5,
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0, 0, 0, 0, 0, 0)
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XTREG(77, 308, 19, 4, 4, 0x02c6, 0x0007, -2, 2, 0x1000, eps6,
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0, 0, 0, 0, 0, 0)
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XTREG(78, 312, 19, 4, 4, 0x02c7, 0x0007, -2, 2, 0x1000, eps7,
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0, 0, 0, 0, 0, 0)
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XTREG(79, 316, 32, 4, 4, 0x02d1, 0x0007, -2, 2, 0x1000, excsave1,
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0, 0, 0, 0, 0, 0)
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XTREG(80, 320, 32, 4, 4, 0x02d2, 0x0007, -2, 2, 0x1000, excsave2,
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0, 0, 0, 0, 0, 0)
|
||||
XTREG(81, 324, 32, 4, 4, 0x02d3, 0x0007, -2, 2, 0x1000, excsave3,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(82, 328, 32, 4, 4, 0x02d4, 0x0007, -2, 2, 0x1000, excsave4,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(83, 332, 32, 4, 4, 0x02d5, 0x0007, -2, 2, 0x1000, excsave5,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(84, 336, 32, 4, 4, 0x02d6, 0x0007, -2, 2, 0x1000, excsave6,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(85, 340, 32, 4, 4, 0x02d7, 0x0007, -2, 2, 0x1000, excsave7,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(86, 344, 8, 4, 4, 0x02e0, 0x0007, -2, 2, 0x1000, cpenable,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(87, 348, 22, 4, 4, 0x02e2, 0x000b, -2, 2, 0x1000, interrupt,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(88, 352, 22, 4, 4, 0x02e2, 0x000d, -2, 2, 0x1000, intset,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(89, 356, 22, 4, 4, 0x02e3, 0x000d, -2, 2, 0x1000, intclear,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(90, 360, 22, 4, 4, 0x02e4, 0x0007, -2, 2, 0x1000, intenable,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(91, 364, 32, 4, 4, 0x02e7, 0x0007, -2, 2, 0x1000, vecbase,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(92, 368, 6, 4, 4, 0x02e8, 0x0007, -2, 2, 0x1000, exccause,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(93, 372, 12, 4, 4, 0x02e9, 0x0003, -2, 2, 0x1000, debugcause,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(94, 376, 32, 4, 4, 0x02ea, 0x000f, -2, 2, 0x1000, ccount,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(95, 380, 32, 4, 4, 0x02eb, 0x0003, -2, 2, 0x1000, prid,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(96, 384, 32, 4, 4, 0x02ec, 0x000f, -2, 2, 0x1000, icount,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(97, 388, 4, 4, 4, 0x02ed, 0x0007, -2, 2, 0x1000, icountlevel,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(98, 392, 32, 4, 4, 0x02ee, 0x0007, -2, 2, 0x1000, excvaddr,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(99, 396, 32, 4, 4, 0x02f0, 0x000f, -2, 2, 0x1000, ccompare0,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(100, 400, 32, 4, 4, 0x02f1, 0x000f, -2, 2, 0x1000, ccompare1,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(101, 404, 32, 4, 4, 0x02f2, 0x000f, -2, 2, 0x1000, ccompare2,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(102, 408, 32, 4, 4, 0x02f4, 0x0007, -2, 2, 0x1000, misc0,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(103, 412, 32, 4, 4, 0x02f5, 0x0007, -2, 2, 0x1000, misc1,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(104, 416, 32, 4, 4, 0x0000, 0x0006, -2, 8, 0x0100, a0,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(105, 420, 32, 4, 4, 0x0001, 0x0006, -2, 8, 0x0100, a1,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(106, 424, 32, 4, 4, 0x0002, 0x0006, -2, 8, 0x0100, a2,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(107, 428, 32, 4, 4, 0x0003, 0x0006, -2, 8, 0x0100, a3,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(108, 432, 32, 4, 4, 0x0004, 0x0006, -2, 8, 0x0100, a4,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(109, 436, 32, 4, 4, 0x0005, 0x0006, -2, 8, 0x0100, a5,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(110, 440, 32, 4, 4, 0x0006, 0x0006, -2, 8, 0x0100, a6,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(111, 444, 32, 4, 4, 0x0007, 0x0006, -2, 8, 0x0100, a7,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(112, 448, 32, 4, 4, 0x0008, 0x0006, -2, 8, 0x0100, a8,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(113, 452, 32, 4, 4, 0x0009, 0x0006, -2, 8, 0x0100, a9,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(114, 456, 32, 4, 4, 0x000a, 0x0006, -2, 8, 0x0100, a10,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(115, 460, 32, 4, 4, 0x000b, 0x0006, -2, 8, 0x0100, a11,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(116, 464, 32, 4, 4, 0x000c, 0x0006, -2, 8, 0x0100, a12,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(117, 468, 32, 4, 4, 0x000d, 0x0006, -2, 8, 0x0100, a13,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(118, 472, 32, 4, 4, 0x000e, 0x0006, -2, 8, 0x0100, a14,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
XTREG(119, 476, 32, 4, 4, 0x000f, 0x0006, -2, 8, 0x0100, a15,
|
||||
0, 0, 0, 0, 0, 0)
|
||||
|
|
@ -107,6 +107,174 @@ static const XtensaConfig core_config[] = {
|
|||
[0] = 0,
|
||||
},
|
||||
.clock_freq_khz = 912000,
|
||||
}, {
|
||||
.name = "dc232b",
|
||||
.options = -1 ^
|
||||
(XTENSA_OPTION_BIT(XTENSA_OPTION_HW_ALIGNMENT) |
|
||||
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
|
||||
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION)),
|
||||
.gdb_regmap = {
|
||||
.num_regs = 120,
|
||||
.num_core_regs = 52,
|
||||
.reg = {
|
||||
#include "gdb-config-dc232b.c"
|
||||
}
|
||||
},
|
||||
.nareg = 32,
|
||||
.ndepc = 1,
|
||||
.excm_level = 3,
|
||||
.vecbase = 0xd0000000,
|
||||
.exception_vector = {
|
||||
[EXC_RESET] = 0xfe000000,
|
||||
[EXC_WINDOW_OVERFLOW4] = 0xd0000000,
|
||||
[EXC_WINDOW_UNDERFLOW4] = 0xd0000040,
|
||||
[EXC_WINDOW_OVERFLOW8] = 0xd0000080,
|
||||
[EXC_WINDOW_UNDERFLOW8] = 0xd00000c0,
|
||||
[EXC_WINDOW_OVERFLOW12] = 0xd0000100,
|
||||
[EXC_WINDOW_UNDERFLOW12] = 0xd0000140,
|
||||
[EXC_KERNEL] = 0xd0000300,
|
||||
[EXC_USER] = 0xd0000340,
|
||||
[EXC_DOUBLE] = 0xd00003c0,
|
||||
},
|
||||
.ninterrupt = 22,
|
||||
.nlevel = 6,
|
||||
.interrupt_vector = {
|
||||
0,
|
||||
0,
|
||||
0xd0000180,
|
||||
0xd00001c0,
|
||||
0xd0000200,
|
||||
0xd0000240,
|
||||
0xd0000280,
|
||||
0xd00002c0,
|
||||
},
|
||||
.level_mask = {
|
||||
[1] = 0x1f80ff,
|
||||
[2] = 0x000100,
|
||||
[3] = 0x200e00,
|
||||
[4] = 0x001000,
|
||||
[5] = 0x002000,
|
||||
[6] = 0x000000,
|
||||
[7] = 0x004000,
|
||||
},
|
||||
.inttype_mask = {
|
||||
[INTTYPE_EDGE] = 0x3f8000,
|
||||
[INTTYPE_NMI] = 0x4000,
|
||||
[INTTYPE_SOFTWARE] = 0x880,
|
||||
},
|
||||
.interrupt = {
|
||||
[0] = {
|
||||
.level = 1,
|
||||
.inttype = INTTYPE_LEVEL,
|
||||
},
|
||||
[1] = {
|
||||
.level = 1,
|
||||
.inttype = INTTYPE_LEVEL,
|
||||
},
|
||||
[2] = {
|
||||
.level = 1,
|
||||
.inttype = INTTYPE_LEVEL,
|
||||
},
|
||||
[3] = {
|
||||
.level = 1,
|
||||
.inttype = INTTYPE_LEVEL,
|
||||
},
|
||||
[4] = {
|
||||
.level = 1,
|
||||
.inttype = INTTYPE_LEVEL,
|
||||
},
|
||||
[5] = {
|
||||
.level = 1,
|
||||
.inttype = INTTYPE_LEVEL,
|
||||
},
|
||||
[6] = {
|
||||
.level = 1,
|
||||
.inttype = INTTYPE_TIMER,
|
||||
},
|
||||
[7] = {
|
||||
.level = 1,
|
||||
.inttype = INTTYPE_SOFTWARE,
|
||||
},
|
||||
[8] = {
|
||||
.level = 2,
|
||||
.inttype = INTTYPE_LEVEL,
|
||||
},
|
||||
[9] = {
|
||||
.level = 3,
|
||||
.inttype = INTTYPE_LEVEL,
|
||||
},
|
||||
[10] = {
|
||||
.level = 3,
|
||||
.inttype = INTTYPE_TIMER,
|
||||
},
|
||||
[11] = {
|
||||
.level = 3,
|
||||
.inttype = INTTYPE_SOFTWARE,
|
||||
},
|
||||
[12] = {
|
||||
.level = 4,
|
||||
.inttype = INTTYPE_LEVEL,
|
||||
},
|
||||
[13] = {
|
||||
.level = 5,
|
||||
.inttype = INTTYPE_TIMER,
|
||||
},
|
||||
[14] = {
|
||||
.level = 7,
|
||||
.inttype = INTTYPE_NMI,
|
||||
},
|
||||
[15] = {
|
||||
.level = 1,
|
||||
.inttype = INTTYPE_EDGE,
|
||||
},
|
||||
[16] = {
|
||||
.level = 1,
|
||||
.inttype = INTTYPE_EDGE,
|
||||
},
|
||||
[17] = {
|
||||
.level = 1,
|
||||
.inttype = INTTYPE_EDGE,
|
||||
},
|
||||
[18] = {
|
||||
.level = 1,
|
||||
.inttype = INTTYPE_EDGE,
|
||||
},
|
||||
[19] = {
|
||||
.level = 1,
|
||||
.inttype = INTTYPE_EDGE,
|
||||
},
|
||||
[20] = {
|
||||
.level = 1,
|
||||
.inttype = INTTYPE_EDGE,
|
||||
},
|
||||
[21] = {
|
||||
.level = 3,
|
||||
.inttype = INTTYPE_EDGE,
|
||||
},
|
||||
},
|
||||
.nccompare = 3,
|
||||
.timerint = {
|
||||
[0] = 6,
|
||||
[1] = 10,
|
||||
[2] = 13,
|
||||
},
|
||||
.clock_freq_khz = 912000,
|
||||
.itlb = {
|
||||
.nways = 7,
|
||||
.way_size = {
|
||||
4, 4, 4, 4, 4, 2, 2,
|
||||
},
|
||||
.varway56 = false,
|
||||
.nrefillentries = 16,
|
||||
},
|
||||
.dtlb = {
|
||||
.nways = 10,
|
||||
.way_size = {
|
||||
4, 4, 4, 4, 4, 2, 2, 1, 1, 1,
|
||||
},
|
||||
.varway56 = false,
|
||||
.nrefillentries = 16,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue