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hw/net/allwinner-sun8i-emac: Use AddressSpace for DMA transfers
Allow the device to execute the DMA transfers in a different AddressSpace. The H3 SoC keeps using the system_memory address space, but via the proper dma_memory_access() API. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20200814122907.27732-1-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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b3aec952bf
commit
4757cb8579
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@ -365,6 +365,8 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
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qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
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qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
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}
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object_property_set_link(OBJECT(&s->emac), "dma-memory",
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OBJECT(get_system_memory()), &error_fatal);
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sysbus_realize(SYS_BUS_DEVICE(&s->emac), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
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@ -19,6 +19,7 @@
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "net/net.h"
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@ -29,6 +30,7 @@
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#include "net/checksum.h"
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#include "qemu/module.h"
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#include "exec/cpu-common.h"
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#include "sysemu/dma.h"
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#include "hw/net/allwinner-sun8i-emac.h"
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/* EMAC register offsets */
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@ -337,12 +339,13 @@ static void allwinner_sun8i_emac_update_irq(AwSun8iEmacState *s)
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qemu_set_irq(s->irq, (s->int_sta & s->int_en) != 0);
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}
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static uint32_t allwinner_sun8i_emac_next_desc(FrameDescriptor *desc,
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static uint32_t allwinner_sun8i_emac_next_desc(AwSun8iEmacState *s,
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FrameDescriptor *desc,
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size_t min_size)
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{
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uint32_t paddr = desc->next;
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cpu_physical_memory_read(paddr, desc, sizeof(*desc));
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dma_memory_read(&s->dma_as, paddr, desc, sizeof(*desc));
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if ((desc->status & DESC_STATUS_CTL) &&
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(desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
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@ -352,7 +355,8 @@ static uint32_t allwinner_sun8i_emac_next_desc(FrameDescriptor *desc,
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}
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}
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static uint32_t allwinner_sun8i_emac_get_desc(FrameDescriptor *desc,
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static uint32_t allwinner_sun8i_emac_get_desc(AwSun8iEmacState *s,
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FrameDescriptor *desc,
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uint32_t start_addr,
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size_t min_size)
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{
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@ -360,7 +364,7 @@ static uint32_t allwinner_sun8i_emac_get_desc(FrameDescriptor *desc,
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/* Note that the list is a cycle. Last entry points back to the head. */
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while (desc_addr != 0) {
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cpu_physical_memory_read(desc_addr, desc, sizeof(*desc));
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dma_memory_read(&s->dma_as, desc_addr, desc, sizeof(*desc));
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if ((desc->status & DESC_STATUS_CTL) &&
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(desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
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@ -379,20 +383,21 @@ static uint32_t allwinner_sun8i_emac_rx_desc(AwSun8iEmacState *s,
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FrameDescriptor *desc,
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size_t min_size)
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{
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return allwinner_sun8i_emac_get_desc(desc, s->rx_desc_curr, min_size);
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return allwinner_sun8i_emac_get_desc(s, desc, s->rx_desc_curr, min_size);
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}
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static uint32_t allwinner_sun8i_emac_tx_desc(AwSun8iEmacState *s,
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FrameDescriptor *desc,
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size_t min_size)
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{
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return allwinner_sun8i_emac_get_desc(desc, s->tx_desc_head, min_size);
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return allwinner_sun8i_emac_get_desc(s, desc, s->tx_desc_head, min_size);
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}
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static void allwinner_sun8i_emac_flush_desc(FrameDescriptor *desc,
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static void allwinner_sun8i_emac_flush_desc(AwSun8iEmacState *s,
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FrameDescriptor *desc,
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uint32_t phys_addr)
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{
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cpu_physical_memory_write(phys_addr, desc, sizeof(*desc));
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dma_memory_write(&s->dma_as, phys_addr, desc, sizeof(*desc));
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}
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static bool allwinner_sun8i_emac_can_receive(NetClientState *nc)
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@ -450,8 +455,8 @@ static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc,
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<< RX_DESC_STATUS_FRM_LEN_SHIFT;
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}
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cpu_physical_memory_write(desc.addr, buf, desc_bytes);
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allwinner_sun8i_emac_flush_desc(&desc, s->rx_desc_curr);
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dma_memory_write(&s->dma_as, desc.addr, buf, desc_bytes);
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allwinner_sun8i_emac_flush_desc(s, &desc, s->rx_desc_curr);
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trace_allwinner_sun8i_emac_receive(s->rx_desc_curr, desc.addr,
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desc_bytes);
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@ -465,7 +470,7 @@ static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc,
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bytes_left -= desc_bytes;
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/* Move to the next descriptor */
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s->rx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 64);
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s->rx_desc_curr = allwinner_sun8i_emac_next_desc(s, &desc, 64);
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if (!s->rx_desc_curr) {
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/* Not enough buffer space available */
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s->int_sta |= INT_STA_RX_BUF_UA;
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@ -501,10 +506,10 @@ static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s)
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desc.status |= TX_DESC_STATUS_LENGTH_ERR;
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break;
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}
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cpu_physical_memory_read(desc.addr, packet_buf + packet_bytes, bytes);
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dma_memory_read(&s->dma_as, desc.addr, packet_buf + packet_bytes, bytes);
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packet_bytes += bytes;
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desc.status &= ~DESC_STATUS_CTL;
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allwinner_sun8i_emac_flush_desc(&desc, s->tx_desc_curr);
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allwinner_sun8i_emac_flush_desc(s, &desc, s->tx_desc_curr);
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/* After the last descriptor, send the packet */
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if (desc.status2 & TX_DESC_STATUS2_LAST_DESC) {
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@ -519,7 +524,7 @@ static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s)
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packet_bytes = 0;
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transmitted++;
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}
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s->tx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 0);
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s->tx_desc_curr = allwinner_sun8i_emac_next_desc(s, &desc, 0);
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}
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/* Raise transmit completed interrupt */
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@ -623,7 +628,7 @@ static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset,
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break;
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case REG_TX_CUR_BUF: /* Transmit Current Buffer */
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if (s->tx_desc_curr != 0) {
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cpu_physical_memory_read(s->tx_desc_curr, &desc, sizeof(desc));
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dma_memory_read(&s->dma_as, s->tx_desc_curr, &desc, sizeof(desc));
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value = desc.addr;
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} else {
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value = 0;
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@ -636,7 +641,7 @@ static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset,
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break;
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case REG_RX_CUR_BUF: /* Receive Current Buffer */
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if (s->rx_desc_curr != 0) {
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cpu_physical_memory_read(s->rx_desc_curr, &desc, sizeof(desc));
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dma_memory_read(&s->dma_as, s->rx_desc_curr, &desc, sizeof(desc));
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value = desc.addr;
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} else {
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value = 0;
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@ -790,6 +795,13 @@ static void allwinner_sun8i_emac_realize(DeviceState *dev, Error **errp)
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{
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AwSun8iEmacState *s = AW_SUN8I_EMAC(dev);
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if (!s->dma_mr) {
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error_setg(errp, TYPE_AW_SUN8I_EMAC " 'dma-memory' link not set");
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return;
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}
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address_space_init(&s->dma_as, s->dma_mr, "emac-dma");
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qemu_macaddr_default_if_unset(&s->conf.macaddr);
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s->nic = qemu_new_nic(&net_allwinner_sun8i_emac_info, &s->conf,
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object_get_typename(OBJECT(dev)), dev->id, s);
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@ -799,6 +811,8 @@ static void allwinner_sun8i_emac_realize(DeviceState *dev, Error **errp)
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static Property allwinner_sun8i_emac_properties[] = {
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DEFINE_NIC_PROPERTIES(AwSun8iEmacState, conf),
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DEFINE_PROP_UINT8("phy-addr", AwSun8iEmacState, mii_phy_addr, 0),
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DEFINE_PROP_LINK("dma-memory", AwSun8iEmacState, dma_mr,
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TYPE_MEMORY_REGION, MemoryRegion *),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -49,6 +49,12 @@ typedef struct AwSun8iEmacState {
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/** Interrupt output signal to notify CPU */
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qemu_irq irq;
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/** Memory region where DMA transfers are done */
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MemoryRegion *dma_mr;
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/** Address space used internally for DMA transfers */
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AddressSpace dma_as;
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/** Generic Network Interface Controller (NIC) for networking API */
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NICState *nic;
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