mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-11-05 20:35:44 +00:00
vm86 emulation closer to Linux kernel code - added correct IRQ emulation for dosemu
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@136 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
89e957e7a2
commit
46ddf5511d
1 changed files with 407 additions and 0 deletions
407
linux-user/vm86.c
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407
linux-user/vm86.c
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/*
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* vm86 linux syscall support
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include <errno.h>
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#include <unistd.h>
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#include "qemu.h"
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//#define DEBUG_VM86
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#define set_flags(X,new,mask) \
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((X) = ((X) & ~(mask)) | ((new) & (mask)))
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#define SAFE_MASK (0xDD5)
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#define RETURN_MASK (0xDFF)
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static inline int is_revectored(int nr, struct target_revectored_struct *bitmap)
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{
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return (tswap32(bitmap->__map[nr >> 5]) >> (nr & 0x1f)) & 1;
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}
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static inline void vm_putw(uint8_t *segptr, unsigned int reg16, unsigned int val)
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{
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*(uint16_t *)(segptr + (reg16 & 0xffff)) = tswap16(val);
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}
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static inline void vm_putl(uint8_t *segptr, unsigned int reg16, unsigned int val)
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{
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*(uint32_t *)(segptr + (reg16 & 0xffff)) = tswap32(val);
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}
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static inline unsigned int vm_getw(uint8_t *segptr, unsigned int reg16)
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{
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return tswap16(*(uint16_t *)(segptr + (reg16 & 0xffff)));
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}
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static inline unsigned int vm_getl(uint8_t *segptr, unsigned int reg16)
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{
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return tswap32(*(uint16_t *)(segptr + (reg16 & 0xffff)));
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}
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void save_v86_state(CPUX86State *env)
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{
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TaskState *ts = env->opaque;
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/* put the VM86 registers in the userspace register structure */
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ts->target_v86->regs.eax = tswap32(env->regs[R_EAX]);
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ts->target_v86->regs.ebx = tswap32(env->regs[R_EBX]);
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ts->target_v86->regs.ecx = tswap32(env->regs[R_ECX]);
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ts->target_v86->regs.edx = tswap32(env->regs[R_EDX]);
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ts->target_v86->regs.esi = tswap32(env->regs[R_ESI]);
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ts->target_v86->regs.edi = tswap32(env->regs[R_EDI]);
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ts->target_v86->regs.ebp = tswap32(env->regs[R_EBP]);
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ts->target_v86->regs.esp = tswap32(env->regs[R_ESP]);
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ts->target_v86->regs.eip = tswap32(env->eip);
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ts->target_v86->regs.cs = tswap16(env->segs[R_CS]);
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ts->target_v86->regs.ss = tswap16(env->segs[R_SS]);
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ts->target_v86->regs.ds = tswap16(env->segs[R_DS]);
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ts->target_v86->regs.es = tswap16(env->segs[R_ES]);
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ts->target_v86->regs.fs = tswap16(env->segs[R_FS]);
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ts->target_v86->regs.gs = tswap16(env->segs[R_GS]);
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set_flags(env->eflags, ts->v86flags, VIF_MASK | ts->v86mask);
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ts->target_v86->regs.eflags = tswap32(env->eflags);
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#ifdef DEBUG_VM86
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fprintf(logfile, "save_v86_state: eflags=%08x cs:ip=%04x:%04x\n",
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env->eflags, env->segs[R_CS], env->eip);
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#endif
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/* restore 32 bit registers */
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env->regs[R_EAX] = ts->vm86_saved_regs.eax;
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env->regs[R_EBX] = ts->vm86_saved_regs.ebx;
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env->regs[R_ECX] = ts->vm86_saved_regs.ecx;
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env->regs[R_EDX] = ts->vm86_saved_regs.edx;
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env->regs[R_ESI] = ts->vm86_saved_regs.esi;
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env->regs[R_EDI] = ts->vm86_saved_regs.edi;
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env->regs[R_EBP] = ts->vm86_saved_regs.ebp;
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env->regs[R_ESP] = ts->vm86_saved_regs.esp;
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env->eflags = ts->vm86_saved_regs.eflags;
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env->eip = ts->vm86_saved_regs.eip;
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cpu_x86_load_seg(env, R_CS, ts->vm86_saved_regs.cs);
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cpu_x86_load_seg(env, R_SS, ts->vm86_saved_regs.ss);
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cpu_x86_load_seg(env, R_DS, ts->vm86_saved_regs.ds);
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cpu_x86_load_seg(env, R_ES, ts->vm86_saved_regs.es);
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cpu_x86_load_seg(env, R_FS, ts->vm86_saved_regs.fs);
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cpu_x86_load_seg(env, R_GS, ts->vm86_saved_regs.gs);
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}
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/* return from vm86 mode to 32 bit. The vm86() syscall will return
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'retval' */
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static inline void return_to_32bit(CPUX86State *env, int retval)
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{
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#ifdef DEBUG_VM86
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fprintf(logfile, "return_to_32bit: ret=0x%x\n", retval);
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#endif
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save_v86_state(env);
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env->regs[R_EAX] = retval;
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}
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static inline int set_IF(CPUX86State *env)
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{
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TaskState *ts = env->opaque;
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ts->v86flags |= VIF_MASK;
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if (ts->v86flags & VIP_MASK) {
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return_to_32bit(env, TARGET_VM86_STI);
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return 1;
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}
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return 0;
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}
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static inline void clear_IF(CPUX86State *env)
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{
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TaskState *ts = env->opaque;
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ts->v86flags &= ~VIF_MASK;
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}
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static inline void clear_TF(CPUX86State *env)
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{
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env->eflags &= ~TF_MASK;
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}
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static inline int set_vflags_long(unsigned long eflags, CPUX86State *env)
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{
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TaskState *ts = env->opaque;
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set_flags(ts->v86flags, eflags, ts->v86mask);
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set_flags(env->eflags, eflags, SAFE_MASK);
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if (eflags & IF_MASK)
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return set_IF(env);
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return 0;
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}
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static inline int set_vflags_short(unsigned short flags, CPUX86State *env)
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{
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TaskState *ts = env->opaque;
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set_flags(ts->v86flags, flags, ts->v86mask & 0xffff);
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set_flags(env->eflags, flags, SAFE_MASK);
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if (flags & IF_MASK)
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return set_IF(env);
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return 0;
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}
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static inline unsigned int get_vflags(CPUX86State *env)
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{
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TaskState *ts = env->opaque;
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unsigned int flags;
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flags = env->eflags & RETURN_MASK;
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if (ts->v86flags & VIF_MASK)
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flags |= IF_MASK;
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return flags | (ts->v86flags & ts->v86mask);
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}
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#define ADD16(reg, val) reg = (reg & ~0xffff) | ((reg + (val)) & 0xffff)
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/* handle VM86 interrupt (NOTE: the CPU core currently does not
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support TSS interrupt revectoring, so this code is always executed) */
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void do_int(CPUX86State *env, int intno)
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{
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TaskState *ts = env->opaque;
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uint32_t *int_ptr, segoffs;
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uint8_t *ssp;
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unsigned int sp;
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#if 1
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if (intno == 0xe6 && (env->regs[R_EAX] & 0xffff) == 0x00c0)
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loglevel = 1;
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#endif
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if (env->segs[R_CS] == TARGET_BIOSSEG)
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goto cannot_handle;
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if (is_revectored(intno, &ts->target_v86->int_revectored))
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goto cannot_handle;
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if (intno == 0x21 && is_revectored((env->regs[R_EAX] >> 8) & 0xff,
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&ts->target_v86->int21_revectored))
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goto cannot_handle;
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int_ptr = (uint32_t *)(intno << 2);
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segoffs = tswap32(*int_ptr);
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if ((segoffs >> 16) == TARGET_BIOSSEG)
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goto cannot_handle;
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#if defined(DEBUG_VM86)
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fprintf(logfile, "VM86: emulating int 0x%x. CS:IP=%04x:%04x\n",
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intno, segoffs >> 16, segoffs & 0xffff);
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#endif
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/* save old state */
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ssp = (uint8_t *)(env->segs[R_SS] << 4);
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sp = env->regs[R_ESP] & 0xffff;
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vm_putw(ssp, sp - 2, get_vflags(env));
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vm_putw(ssp, sp - 4, env->segs[R_CS]);
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vm_putw(ssp, sp - 6, env->eip);
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ADD16(env->regs[R_ESP], -6);
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/* goto interrupt handler */
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env->eip = segoffs & 0xffff;
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cpu_x86_load_seg(env, R_CS, segoffs >> 16);
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clear_TF(env);
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clear_IF(env);
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return;
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cannot_handle:
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#if defined(DEBUG_VM86)
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fprintf(logfile, "VM86: return to 32 bits int 0x%x\n", intno);
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#endif
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return_to_32bit(env, TARGET_VM86_INTx | (intno << 8));
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}
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#define CHECK_IF_IN_TRAP(disp) \
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if ((tswap32(ts->target_v86->vm86plus.flags) & TARGET_vm86dbg_active) && \
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(tswap32(ts->target_v86->vm86plus.flags) & TARGET_vm86dbg_TFpendig)) \
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vm_putw(ssp,sp + disp,vm_getw(ssp,sp + disp) | TF_MASK)
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#define VM86_FAULT_RETURN \
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if ((tswap32(ts->target_v86->vm86plus.flags) & TARGET_force_return_for_pic) && \
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(ts->v86flags & (IF_MASK | VIF_MASK))) \
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return_to_32bit(env, TARGET_VM86_PICRETURN); \
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return
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void handle_vm86_fault(CPUX86State *env)
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{
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TaskState *ts = env->opaque;
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uint8_t *csp, *pc, *ssp;
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unsigned int ip, sp;
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csp = (uint8_t *)(env->segs[R_CS] << 4);
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ip = env->eip & 0xffff;
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pc = csp + ip;
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ssp = (uint8_t *)(env->segs[R_SS] << 4);
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sp = env->regs[R_ESP] & 0xffff;
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#if defined(DEBUG_VM86)
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fprintf(logfile, "VM86 exception %04x:%08x %02x %02x\n",
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env->segs[R_CS], env->eip, pc[0], pc[1]);
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#endif
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/* VM86 mode */
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switch(pc[0]) {
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case 0x66:
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switch(pc[1]) {
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case 0x9c: /* pushfd */
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ADD16(env->eip, 2);
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ADD16(env->regs[R_ESP], -4);
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vm_putl(ssp, sp - 4, get_vflags(env));
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VM86_FAULT_RETURN;
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case 0x9d: /* popfd */
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ADD16(env->eip, 2);
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ADD16(env->regs[R_ESP], 4);
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CHECK_IF_IN_TRAP(0);
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if (set_vflags_long(vm_getl(ssp, sp), env))
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return;
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VM86_FAULT_RETURN;
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case 0xcf: /* iretd */
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ADD16(env->regs[R_ESP], 12);
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env->eip = vm_getl(ssp, sp) & 0xffff;
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cpu_x86_load_seg(env, R_CS, vm_getl(ssp, sp + 4) & 0xffff);
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CHECK_IF_IN_TRAP(8);
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if (set_vflags_long(vm_getl(ssp, sp + 8), env))
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return;
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VM86_FAULT_RETURN;
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default:
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goto vm86_gpf;
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}
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break;
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case 0x9c: /* pushf */
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ADD16(env->eip, 1);
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ADD16(env->regs[R_ESP], -2);
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vm_putw(ssp, sp - 2, get_vflags(env));
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VM86_FAULT_RETURN;
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case 0x9d: /* popf */
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ADD16(env->eip, 1);
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ADD16(env->regs[R_ESP], 2);
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CHECK_IF_IN_TRAP(0);
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if (set_vflags_short(vm_getw(ssp, sp), env))
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return;
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VM86_FAULT_RETURN;
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case 0xcd: /* int */
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ADD16(env->eip, 2);
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do_int(env, pc[1]);
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break;
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case 0xcf: /* iret */
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ADD16(env->regs[R_ESP], 6);
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env->eip = vm_getw(ssp, sp);
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cpu_x86_load_seg(env, R_CS, vm_getw(ssp, sp + 2));
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CHECK_IF_IN_TRAP(4);
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if (set_vflags_short(vm_getw(ssp, sp + 4), env))
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return;
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VM86_FAULT_RETURN;
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case 0xfa: /* cli */
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ADD16(env->eip, 1);
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clear_IF(env);
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VM86_FAULT_RETURN;
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case 0xfb: /* sti */
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ADD16(env->eip, 1);
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if (set_IF(env))
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return;
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VM86_FAULT_RETURN;
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default:
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vm86_gpf:
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/* real VM86 GPF exception */
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return_to_32bit(env, TARGET_VM86_UNKNOWN);
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break;
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}
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}
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int do_vm86(CPUX86State *env, long subfunction,
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struct target_vm86plus_struct * target_v86)
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{
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TaskState *ts = env->opaque;
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int ret;
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switch (subfunction) {
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case TARGET_VM86_REQUEST_IRQ:
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case TARGET_VM86_FREE_IRQ:
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case TARGET_VM86_GET_IRQ_BITS:
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case TARGET_VM86_GET_AND_RESET_IRQ:
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gemu_log("qemu: unsupported vm86 subfunction (%ld)\n", subfunction);
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ret = -EINVAL;
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goto out;
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case TARGET_VM86_PLUS_INSTALL_CHECK:
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/* NOTE: on old vm86 stuff this will return the error
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from verify_area(), because the subfunction is
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interpreted as (invalid) address to vm86_struct.
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So the installation check works.
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*/
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ret = 0;
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goto out;
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}
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ts->target_v86 = target_v86;
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/* save current CPU regs */
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ts->vm86_saved_regs.eax = 0; /* default vm86 syscall return code */
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ts->vm86_saved_regs.ebx = env->regs[R_EBX];
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ts->vm86_saved_regs.ecx = env->regs[R_ECX];
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ts->vm86_saved_regs.edx = env->regs[R_EDX];
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ts->vm86_saved_regs.esi = env->regs[R_ESI];
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ts->vm86_saved_regs.edi = env->regs[R_EDI];
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ts->vm86_saved_regs.ebp = env->regs[R_EBP];
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ts->vm86_saved_regs.esp = env->regs[R_ESP];
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ts->vm86_saved_regs.eflags = env->eflags;
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ts->vm86_saved_regs.eip = env->eip;
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ts->vm86_saved_regs.cs = env->segs[R_CS];
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ts->vm86_saved_regs.ss = env->segs[R_SS];
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ts->vm86_saved_regs.ds = env->segs[R_DS];
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ts->vm86_saved_regs.es = env->segs[R_ES];
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ts->vm86_saved_regs.fs = env->segs[R_FS];
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ts->vm86_saved_regs.gs = env->segs[R_GS];
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/* build vm86 CPU state */
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ts->v86flags = tswap32(target_v86->regs.eflags);
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env->eflags = (env->eflags & ~SAFE_MASK) |
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(tswap32(target_v86->regs.eflags) & SAFE_MASK) | VM_MASK;
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ts->v86mask = ID_MASK | AC_MASK | NT_MASK | IOPL_MASK;
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env->regs[R_EBX] = tswap32(target_v86->regs.ebx);
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env->regs[R_ECX] = tswap32(target_v86->regs.ecx);
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env->regs[R_EDX] = tswap32(target_v86->regs.edx);
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env->regs[R_ESI] = tswap32(target_v86->regs.esi);
|
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env->regs[R_EDI] = tswap32(target_v86->regs.edi);
|
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env->regs[R_EBP] = tswap32(target_v86->regs.ebp);
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env->regs[R_ESP] = tswap32(target_v86->regs.esp);
|
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env->eip = tswap32(target_v86->regs.eip);
|
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cpu_x86_load_seg(env, R_CS, tswap16(target_v86->regs.cs));
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cpu_x86_load_seg(env, R_SS, tswap16(target_v86->regs.ss));
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cpu_x86_load_seg(env, R_DS, tswap16(target_v86->regs.ds));
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cpu_x86_load_seg(env, R_ES, tswap16(target_v86->regs.es));
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cpu_x86_load_seg(env, R_FS, tswap16(target_v86->regs.fs));
|
||||
cpu_x86_load_seg(env, R_GS, tswap16(target_v86->regs.gs));
|
||||
ret = tswap32(target_v86->regs.eax); /* eax will be restored at
|
||||
the end of the syscall */
|
||||
#ifdef DEBUG_VM86
|
||||
fprintf(logfile, "do_vm86: cs:ip=%04x:%04x\n", env->segs[R_CS], env->eip);
|
||||
#endif
|
||||
/* now the virtual CPU is ready for vm86 execution ! */
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
Loading…
Reference in a new issue