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target/arm: Convert T16, load (literal)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-66-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -113,6 +113,10 @@ LDRH_ri 10001 ..... ... ... @ldst_ri_2
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STR_ri 10010 ... ........ @ldst_spec_i rn=13
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LDR_ri 10011 ... ........ @ldst_spec_i rn=13
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# Load (PC-relative)
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LDR_ri 01001 ... ........ @ldst_spec_i rn=15
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# Add PC/SP (immediate)
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ADR 10100 rd:3 ........ imm=%imm8_0x4
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@ -982,14 +982,6 @@ static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
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TCGv_i32 a32, int index) \
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{ \
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gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \
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} \
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static inline void gen_aa32_ld##SUFF##_iss(DisasContext *s, \
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TCGv_i32 val, \
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TCGv_i32 a32, int index, \
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ISSInfo issinfo) \
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{ \
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gen_aa32_ld##SUFF(s, val, a32, index); \
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disas_set_da_iss(s, OPC, issinfo); \
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}
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#define DO_GEN_ST(SUFF, OPC) \
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@ -997,14 +989,6 @@ static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
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TCGv_i32 a32, int index) \
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{ \
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gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \
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} \
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static inline void gen_aa32_st##SUFF##_iss(DisasContext *s, \
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TCGv_i32 val, \
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TCGv_i32 a32, int index, \
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ISSInfo issinfo) \
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{ \
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gen_aa32_st##SUFF(s, val, a32, index); \
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disas_set_da_iss(s, OPC, issinfo | ISSIsWrite); \
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}
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static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val)
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@ -1053,9 +1037,7 @@ static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
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gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data);
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}
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DO_GEN_LD(8s, MO_SB)
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DO_GEN_LD(8u, MO_UB)
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DO_GEN_LD(16s, MO_SW)
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DO_GEN_LD(16u, MO_UW)
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DO_GEN_LD(32u, MO_UL)
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DO_GEN_ST(8, MO_UB)
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@ -10754,11 +10736,10 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
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static void disas_thumb_insn(DisasContext *s, uint32_t insn)
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{
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uint32_t val, rd;
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uint32_t val;
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int32_t offset;
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TCGv_i32 tmp;
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TCGv_i32 tmp2;
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TCGv_i32 addr;
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if (disas_t16(s, insn)) {
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return;
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@ -10768,26 +10749,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
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switch (insn >> 12) {
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case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree */
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case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */
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goto illegal_op;
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case 4:
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if (insn & (1 << 11)) {
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rd = (insn >> 8) & 7;
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/* load pc-relative. Bit 1 of PC is ignored. */
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addr = add_reg_for_lit(s, 15, (insn & 0xff) * 4);
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tmp = tcg_temp_new_i32();
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gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),
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rd | ISSIs16Bit);
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tcg_temp_free_i32(addr);
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store_reg(s, rd, tmp);
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break;
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}
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/*
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* - Data-processing (two low registers), in decodetree
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* - data processing extended, branch and exchange, in decodetree
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*/
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goto illegal_op;
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case 4: /* ldr lit, data proc (2reg), data proc ext, bx; in decodetree */
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case 5: /* load/store register offset, in decodetree */
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case 6: /* load/store word immediate offset, in decodetree */
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case 7: /* load/store byte immediate offset, in decodetree */
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