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target-microblaze: Rework NOP/zero instruction handling
Remove the abort on a sequence of NOP/zero instructions. Always return early and avoid decoding NOP/zero instructions. This fixes Coverity CID 1391443. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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@ -90,7 +90,6 @@ typedef struct DisasContext {
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uint32_t jmp_pc;
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int abort_at_next_insn;
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int nr_nops;
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struct TranslationBlock *tb;
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int singlestep_enabled;
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} DisasContext;
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@ -1576,17 +1575,12 @@ static inline void decode(DisasContext *dc, uint32_t ir)
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dc->ir = ir;
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LOG_DIS("%8.8x\t", dc->ir);
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if (dc->ir)
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dc->nr_nops = 0;
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else {
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if (ir == 0) {
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trap_illegal(dc, dc->cpu->env.pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK);
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LOG_DIS("nr_nops=%d\t", dc->nr_nops);
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dc->nr_nops++;
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if (dc->nr_nops > 4) {
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cpu_abort(CPU(dc->cpu), "fetching nop sequence\n");
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}
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/* Don't decode nop/zero instructions any further. */
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return;
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}
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/* bit 2 seems to indicate insn type. */
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dc->type_b = ir & (1 << 29);
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@ -1633,7 +1627,6 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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dc->singlestep_enabled = cs->singlestep_enabled;
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dc->cpustate_changed = 0;
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dc->abort_at_next_insn = 0;
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dc->nr_nops = 0;
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if (pc_start & 3) {
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cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start);
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