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hw/block/pflash_cfi02: Extract pflash_cfi02_fill_cfi_table()
Fill the CFI table in out of DeviceRealize() in a new function: pflash_cfi02_fill_cfi_table(). Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: David Edmondson <david.edmondson@oracle.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210310170528.1184868-4-philmd@redhat.com>
This commit is contained in:
Philippe Mathieu-Daudé
parent
a42cd11bd3
commit
4586c2e5d5
1 changed files with 99 additions and 94 deletions
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@ -724,6 +724,104 @@ static const MemoryRegionOps pflash_cfi02_ops = {
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void pflash_cfi02_fill_cfi_table(PFlashCFI02 *pfl, int nb_regions)
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{
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/* Hardcoded CFI table (mostly from SG29 Spansion flash) */
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const uint16_t pri_ofs = 0x40;
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/* Standard "QRY" string */
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pfl->cfi_table[0x10] = 'Q';
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pfl->cfi_table[0x11] = 'R';
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pfl->cfi_table[0x12] = 'Y';
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/* Command set (AMD/Fujitsu) */
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pfl->cfi_table[0x13] = 0x02;
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pfl->cfi_table[0x14] = 0x00;
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/* Primary extended table address */
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pfl->cfi_table[0x15] = pri_ofs;
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pfl->cfi_table[0x16] = pri_ofs >> 8;
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/* Alternate command set (none) */
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pfl->cfi_table[0x17] = 0x00;
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pfl->cfi_table[0x18] = 0x00;
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/* Alternate extended table (none) */
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pfl->cfi_table[0x19] = 0x00;
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pfl->cfi_table[0x1A] = 0x00;
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/* Vcc min */
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pfl->cfi_table[0x1B] = 0x27;
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/* Vcc max */
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pfl->cfi_table[0x1C] = 0x36;
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/* Vpp min (no Vpp pin) */
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pfl->cfi_table[0x1D] = 0x00;
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/* Vpp max (no Vpp pin) */
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pfl->cfi_table[0x1E] = 0x00;
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/* Timeout per single byte/word write (128 ms) */
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pfl->cfi_table[0x1F] = 0x07;
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/* Timeout for min size buffer write (NA) */
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pfl->cfi_table[0x20] = 0x00;
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/* Typical timeout for block erase (512 ms) */
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pfl->cfi_table[0x21] = 0x09;
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/* Typical timeout for full chip erase (4096 ms) */
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pfl->cfi_table[0x22] = 0x0C;
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/* Reserved */
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pfl->cfi_table[0x23] = 0x01;
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/* Max timeout for buffer write (NA) */
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pfl->cfi_table[0x24] = 0x00;
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/* Max timeout for block erase */
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pfl->cfi_table[0x25] = 0x0A;
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/* Max timeout for chip erase */
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pfl->cfi_table[0x26] = 0x0D;
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/* Device size */
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pfl->cfi_table[0x27] = ctz32(pfl->chip_len);
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/* Flash device interface (8 & 16 bits) */
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pfl->cfi_table[0x28] = 0x02;
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pfl->cfi_table[0x29] = 0x00;
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/* Max number of bytes in multi-bytes write */
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/*
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* XXX: disable buffered write as it's not supported
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* pfl->cfi_table[0x2A] = 0x05;
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*/
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pfl->cfi_table[0x2A] = 0x00;
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pfl->cfi_table[0x2B] = 0x00;
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/* Number of erase block regions */
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pfl->cfi_table[0x2c] = nb_regions;
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/* Erase block regions */
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for (int i = 0; i < nb_regions; ++i) {
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uint32_t sector_len_per_device = pfl->sector_len[i];
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pfl->cfi_table[0x2d + 4 * i] = pfl->nb_blocs[i] - 1;
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pfl->cfi_table[0x2e + 4 * i] = (pfl->nb_blocs[i] - 1) >> 8;
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pfl->cfi_table[0x2f + 4 * i] = sector_len_per_device >> 8;
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pfl->cfi_table[0x30 + 4 * i] = sector_len_per_device >> 16;
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}
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assert(0x2c + 4 * nb_regions < pri_ofs);
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/* Extended */
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pfl->cfi_table[0x00 + pri_ofs] = 'P';
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pfl->cfi_table[0x01 + pri_ofs] = 'R';
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pfl->cfi_table[0x02 + pri_ofs] = 'I';
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/* Extended version 1.0 */
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pfl->cfi_table[0x03 + pri_ofs] = '1';
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pfl->cfi_table[0x04 + pri_ofs] = '0';
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/* Address sensitive unlock required. */
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pfl->cfi_table[0x05 + pri_ofs] = 0x00;
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/* Erase suspend to read/write. */
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pfl->cfi_table[0x06 + pri_ofs] = 0x02;
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/* Sector protect not supported. */
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pfl->cfi_table[0x07 + pri_ofs] = 0x00;
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/* Temporary sector unprotect not supported. */
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pfl->cfi_table[0x08 + pri_ofs] = 0x00;
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/* Sector protect/unprotect scheme. */
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pfl->cfi_table[0x09 + pri_ofs] = 0x00;
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/* Simultaneous operation not supported. */
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pfl->cfi_table[0x0a + pri_ofs] = 0x00;
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/* Burst mode not supported. */
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pfl->cfi_table[0x0b + pri_ofs] = 0x00;
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/* Page mode not supported. */
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pfl->cfi_table[0x0c + pri_ofs] = 0x00;
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assert(0x0c + pri_ofs < ARRAY_SIZE(pfl->cfi_table));
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}
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static void pflash_cfi02_realize(DeviceState *dev, Error **errp)
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{
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ERRP_GUARD();
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@ -837,100 +935,7 @@ static void pflash_cfi02_realize(DeviceState *dev, Error **errp)
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pfl->cmd = 0;
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pfl->status = 0;
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/* Hardcoded CFI table (mostly from SG29 Spansion flash) */
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const uint16_t pri_ofs = 0x40;
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/* Standard "QRY" string */
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pfl->cfi_table[0x10] = 'Q';
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pfl->cfi_table[0x11] = 'R';
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pfl->cfi_table[0x12] = 'Y';
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/* Command set (AMD/Fujitsu) */
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pfl->cfi_table[0x13] = 0x02;
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pfl->cfi_table[0x14] = 0x00;
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/* Primary extended table address */
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pfl->cfi_table[0x15] = pri_ofs;
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pfl->cfi_table[0x16] = pri_ofs >> 8;
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/* Alternate command set (none) */
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pfl->cfi_table[0x17] = 0x00;
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pfl->cfi_table[0x18] = 0x00;
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/* Alternate extended table (none) */
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pfl->cfi_table[0x19] = 0x00;
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pfl->cfi_table[0x1A] = 0x00;
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/* Vcc min */
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pfl->cfi_table[0x1B] = 0x27;
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/* Vcc max */
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pfl->cfi_table[0x1C] = 0x36;
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/* Vpp min (no Vpp pin) */
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pfl->cfi_table[0x1D] = 0x00;
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/* Vpp max (no Vpp pin) */
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pfl->cfi_table[0x1E] = 0x00;
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/* Timeout per single byte/word write (128 ms) */
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pfl->cfi_table[0x1F] = 0x07;
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/* Timeout for min size buffer write (NA) */
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pfl->cfi_table[0x20] = 0x00;
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/* Typical timeout for block erase (512 ms) */
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pfl->cfi_table[0x21] = 0x09;
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/* Typical timeout for full chip erase (4096 ms) */
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pfl->cfi_table[0x22] = 0x0C;
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/* Reserved */
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pfl->cfi_table[0x23] = 0x01;
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/* Max timeout for buffer write (NA) */
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pfl->cfi_table[0x24] = 0x00;
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/* Max timeout for block erase */
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pfl->cfi_table[0x25] = 0x0A;
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/* Max timeout for chip erase */
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pfl->cfi_table[0x26] = 0x0D;
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/* Device size */
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pfl->cfi_table[0x27] = ctz32(pfl->chip_len);
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/* Flash device interface (8 & 16 bits) */
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pfl->cfi_table[0x28] = 0x02;
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pfl->cfi_table[0x29] = 0x00;
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/* Max number of bytes in multi-bytes write */
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/*
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* XXX: disable buffered write as it's not supported
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* pfl->cfi_table[0x2A] = 0x05;
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*/
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pfl->cfi_table[0x2A] = 0x00;
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pfl->cfi_table[0x2B] = 0x00;
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/* Number of erase block regions */
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pfl->cfi_table[0x2c] = nb_regions;
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/* Erase block regions */
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for (int i = 0; i < nb_regions; ++i) {
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uint32_t sector_len_per_device = pfl->sector_len[i];
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pfl->cfi_table[0x2d + 4 * i] = pfl->nb_blocs[i] - 1;
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pfl->cfi_table[0x2e + 4 * i] = (pfl->nb_blocs[i] - 1) >> 8;
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pfl->cfi_table[0x2f + 4 * i] = sector_len_per_device >> 8;
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pfl->cfi_table[0x30 + 4 * i] = sector_len_per_device >> 16;
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}
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assert(0x2c + 4 * nb_regions < pri_ofs);
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/* Extended */
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pfl->cfi_table[0x00 + pri_ofs] = 'P';
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pfl->cfi_table[0x01 + pri_ofs] = 'R';
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pfl->cfi_table[0x02 + pri_ofs] = 'I';
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/* Extended version 1.0 */
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pfl->cfi_table[0x03 + pri_ofs] = '1';
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pfl->cfi_table[0x04 + pri_ofs] = '0';
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/* Address sensitive unlock required. */
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pfl->cfi_table[0x05 + pri_ofs] = 0x00;
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/* Erase suspend to read/write. */
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pfl->cfi_table[0x06 + pri_ofs] = 0x02;
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/* Sector protect not supported. */
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pfl->cfi_table[0x07 + pri_ofs] = 0x00;
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/* Temporary sector unprotect not supported. */
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pfl->cfi_table[0x08 + pri_ofs] = 0x00;
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/* Sector protect/unprotect scheme. */
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pfl->cfi_table[0x09 + pri_ofs] = 0x00;
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/* Simultaneous operation not supported. */
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pfl->cfi_table[0x0a + pri_ofs] = 0x00;
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/* Burst mode not supported. */
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pfl->cfi_table[0x0b + pri_ofs] = 0x00;
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/* Page mode not supported. */
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pfl->cfi_table[0x0c + pri_ofs] = 0x00;
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assert(0x0c + pri_ofs < ARRAY_SIZE(pfl->cfi_table));
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pflash_cfi02_fill_cfi_table(pfl, nb_regions);
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}
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static Property pflash_cfi02_properties[] = {
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