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hw/misc/mips_cpc: Start vCPU when powered on

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In commit 102ca9667d we set "start-powered-off" on all vCPUs
included in the CPS (Coherent Processing System) but forgot to
start the vCPUS on when they are powered on in the CPC (Cluster
Power Controller).

This fixes the following tests:

  $ avocado run tests/acceptance/machine_mips_malta.py
   (1/3) test_mips_malta_i6400_framebuffer_logo_1core: PASS (3.67 s)
   (2/3) test_mips_malta_i6400_framebuffer_logo_7cores: INTERRUPTED: Test interrupted by SIGTERM (30.22 s)
   (3/3) test_mips_malta_i6400_framebuffer_logo_8cores: INTERRUPTED: Test interrupted by SIGTERM (30.25 s)
  RESULTS    : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 2 | CANCEL 0

Fixes: 102ca9667d ("mips/cps: Use start-powered-off CPUState property")
Reported-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20201007113942.2523866-1-f4bug@amsat.org>
Message-Id: <20201007160038.26953-3-alex.bennee@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2020-10-07 17:00:18 +01:00 committed by Alex Bennée
parent 0c3dd50eae
commit 42a052333a
1 changed files with 1 additions and 0 deletions
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1
hw/misc/mips_cpc.c
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@ -38,6 +38,7 @@ static void mips_cpu_reset_async_work(CPUState *cs, run_on_cpu_data data)
MIPSCPCState *cpc = (MIPSCPCState *) data.host_ptr;
cpu_reset(cs);
cs->halted = 0;
cpc->vp_running |= 1ULL << cs->cpu_index;
}