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target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6
Also consider OPC_SPIM instruction as deleted in R6 because it is overlaping with MIPS32R6 SDBBP. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Leon Alrae
parent
b42ee5e1d9
commit
4267d3e6e0
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@ -1217,6 +1217,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
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them first. The assemblers uses a hash table based on the
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instruction name anyhow. */
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/* name, args, match, mask, pinfo, membership */
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{"clz", "U,s", 0x00000050, 0xfc1f07ff, WR_d|RD_s, 0, I32R6},
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{"clo", "U,s", 0x00000051, 0xfc1f07ff, WR_d|RD_s, 0, I32R6},
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{"dclz", "U,s", 0x00000052, 0xfc1f07ff, WR_d|RD_s, 0, I64R6},
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{"dclo", "U,s", 0x00000053, 0xfc1f07ff, WR_d|RD_s, 0, I64R6},
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{"sdbbp", "B", 0x0000000e, 0xfc00003f, TRAP, 0, I32R6},
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{"mul", "d,s,t", 0x00000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
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{"muh", "d,s,t", 0x000000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
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{"mulu", "d,s,t", 0x00000099, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
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@ -235,6 +235,12 @@ enum {
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R6_OPC_DMOD = OPC_DDIV | (3 << 6),
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R6_OPC_DDIVU = OPC_DDIVU | (2 << 6),
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R6_OPC_DMODU = OPC_DDIVU | (3 << 6),
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R6_OPC_CLZ = 0x10 | OPC_SPECIAL,
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R6_OPC_CLO = 0x11 | OPC_SPECIAL,
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R6_OPC_DCLZ = 0x12 | OPC_SPECIAL,
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R6_OPC_DCLO = 0x13 | OPC_SPECIAL,
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R6_OPC_SDBBP = 0x0e | OPC_SPECIAL,
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};
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/* Multiplication variants of the vr54xx. */
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@ -3263,19 +3269,23 @@ static void gen_cl (DisasContext *ctx, uint32_t opc,
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gen_load_gpr(t0, rs);
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switch (opc) {
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case OPC_CLO:
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case R6_OPC_CLO:
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gen_helper_clo(cpu_gpr[rd], t0);
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opn = "clo";
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break;
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case OPC_CLZ:
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case R6_OPC_CLZ:
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gen_helper_clz(cpu_gpr[rd], t0);
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opn = "clz";
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break;
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#if defined(TARGET_MIPS64)
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case OPC_DCLO:
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case R6_OPC_DCLO:
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gen_helper_dclo(cpu_gpr[rd], t0);
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opn = "dclo";
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break;
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case OPC_DCLZ:
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case R6_OPC_DCLZ:
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gen_helper_dclz(cpu_gpr[rd], t0);
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opn = "dclz";
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break;
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@ -14747,12 +14757,13 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
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static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
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{
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int rs, rt, rd;
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int rs, rt, rd, sa;
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uint32_t op1, op2;
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rs = (ctx->opcode >> 21) & 0x1f;
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rt = (ctx->opcode >> 16) & 0x1f;
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rd = (ctx->opcode >> 11) & 0x1f;
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sa = (ctx->opcode >> 6) & 0x1f;
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op1 = MASK_SPECIAL(ctx->opcode);
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switch (op1) {
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@ -14779,7 +14790,31 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
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case OPC_SELNEZ:
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gen_cond_move(ctx, op1, rd, rs, rt);
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break;
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case R6_OPC_CLO:
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case R6_OPC_CLZ:
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if (rt == 0 && sa == 1) {
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/* Major opcode and function field is shared with preR6 MFHI/MTHI.
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We need additionally to check other fields */
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gen_cl(ctx, op1, rd, rs);
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} else {
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generate_exception(ctx, EXCP_RI);
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}
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break;
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case R6_OPC_SDBBP:
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generate_exception(ctx, EXCP_DBp);
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break;
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#if defined(TARGET_MIPS64)
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case R6_OPC_DCLO:
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case R6_OPC_DCLZ:
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if (rt == 0 && sa == 1) {
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/* Major opcode and function field is shared with preR6 MFHI/MTHI.
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We need additionally to check other fields */
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check_mips_64(ctx);
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gen_cl(ctx, op1, rd, rs);
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} else {
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generate_exception(ctx, EXCP_RI);
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}
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break;
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case OPC_DMULT ... OPC_DDIVU:
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op2 = MASK_R6_MULDIV(ctx->opcode);
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switch (op2) {
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@ -14865,6 +14900,16 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
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gen_muldiv(ctx, op1, 0, rs, rt);
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break;
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#endif
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case OPC_SPIM:
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#ifdef MIPS_STRICT_STANDARD
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MIPS_INVAL("SPIM");
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generate_exception(ctx, EXCP_RI);
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#else
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/* Implemented as RI exception for now. */
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MIPS_INVAL("spim (unofficial)");
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generate_exception(ctx, EXCP_RI);
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#endif
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break;
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default: /* Invalid */
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MIPS_INVAL("special_legacy");
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generate_exception(ctx, EXCP_RI);
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@ -14959,16 +15004,6 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
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case OPC_BREAK:
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generate_exception(ctx, EXCP_BREAK);
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break;
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case OPC_SPIM:
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#ifdef MIPS_STRICT_STANDARD
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MIPS_INVAL("SPIM");
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generate_exception(ctx, EXCP_RI);
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#else
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/* Implemented as RI exception for now. */
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MIPS_INVAL("spim (unofficial)");
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generate_exception(ctx, EXCP_RI);
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#endif
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break;
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case OPC_SYNC:
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/* Treat as NOP. */
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break;
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@ -15058,24 +15093,13 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
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}
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}
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static void decode_opc_special2_r6(CPUMIPSState *env, DisasContext *ctx)
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{
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uint32_t op1;
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op1 = MASK_SPECIAL2(ctx->opcode);
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switch (op1) {
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default: /* Invalid */
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MIPS_INVAL("special2_r6");
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generate_exception(ctx, EXCP_RI);
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break;
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}
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}
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static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
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{
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int rs, rt, rd;
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uint32_t op1;
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check_insn_opc_removed(ctx, ISA_MIPS32R6);
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rs = (ctx->opcode >> 21) & 0x1f;
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rt = (ctx->opcode >> 16) & 0x1f;
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rd = (ctx->opcode >> 11) & 0x1f;
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@ -15099,34 +15123,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
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check_insn(ctx, INSN_LOONGSON2F);
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gen_loongson_integer(ctx, op1, rd, rs, rt);
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break;
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#if defined(TARGET_MIPS64)
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case OPC_DMULT_G_2F:
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case OPC_DMULTU_G_2F:
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case OPC_DDIV_G_2F:
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case OPC_DDIVU_G_2F:
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case OPC_DMOD_G_2F:
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case OPC_DMODU_G_2F:
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check_insn(ctx, INSN_LOONGSON2F);
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gen_loongson_integer(ctx, op1, rd, rs, rt);
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break;
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#endif
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default: /* Invalid */
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MIPS_INVAL("special2_legacy");
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generate_exception(ctx, EXCP_RI);
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break;
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}
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}
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static void decode_opc_special2(CPUMIPSState *env, DisasContext *ctx)
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{
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int rs, rd;
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uint32_t op1;
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rs = (ctx->opcode >> 21) & 0x1f;
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rd = (ctx->opcode >> 11) & 0x1f;
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op1 = MASK_SPECIAL2(ctx->opcode);
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switch (op1) {
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case OPC_CLO:
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case OPC_CLZ:
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check_insn(ctx, ISA_MIPS32);
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@ -15151,13 +15147,20 @@ static void decode_opc_special2(CPUMIPSState *env, DisasContext *ctx)
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check_mips_64(ctx);
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gen_cl(ctx, op1, rd, rs);
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break;
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case OPC_DMULT_G_2F:
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case OPC_DMULTU_G_2F:
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case OPC_DDIV_G_2F:
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case OPC_DDIVU_G_2F:
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case OPC_DMOD_G_2F:
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case OPC_DMODU_G_2F:
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check_insn(ctx, INSN_LOONGSON2F);
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gen_loongson_integer(ctx, op1, rd, rs, rt);
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break;
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#endif
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default:
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if (ctx->insn_flags & ISA_MIPS32R6) {
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decode_opc_special2_r6(env, ctx);
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} else {
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decode_opc_special2_legacy(env, ctx);
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}
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default: /* Invalid */
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MIPS_INVAL("special2_legacy");
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generate_exception(ctx, EXCP_RI);
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break;
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}
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}
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@ -15839,7 +15842,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
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decode_opc_special(env, ctx);
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break;
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case OPC_SPECIAL2:
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decode_opc_special2(env, ctx);
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decode_opc_special2_legacy(env, ctx);
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break;
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case OPC_SPECIAL3:
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decode_opc_special3(env, ctx);
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