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target-alpha: Fix interrupt mask for cpu1

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A typo prevents ISA interrupts from being recognized on cpu0,
which is where the smp kernel normally wants to see them.

Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2016-11-22 16:53:53 +01:00
parent c36ed06e91
commit 424ad8388f
1 changed files with 1 additions and 1 deletions
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2
hw/alpha/typhoon.c
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@ -376,7 +376,7 @@ static void cchip_write(void *opaque, hwaddr addr,
break;
case 0x0240: /* DIM1 */
/* DIM: Device Interrupt Mask Register, CPU1. */
s->cchip.dim[0] = val;
s->cchip.dim[1] = val;
cpu_irq_change(s->cchip.cpu[1], val & s->cchip.drir);
break;