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tcg: Add tcg_gen_gvec_andcs
Add tcg expander and helper functions for and-compliment vector with scalar operand. Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Message-Id: <20230428144757.57530-10-lawrence.hunter@codethink.co.uk> [rth: Split out of larger patch.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -550,6 +550,17 @@ void HELPER(gvec_ands)(void *d, void *a, uint64_t b, uint32_t desc)
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_andcs)(void *d, void *a, uint64_t b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
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*(uint64_t *)(d + i) = *(uint64_t *)(a + i) & ~b;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_xors)(void *d, void *a, uint64_t b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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@ -217,6 +217,7 @@ DEF_HELPER_FLAGS_4(gvec_nor, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_eqv, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_ands, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
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DEF_HELPER_FLAGS_4(gvec_andcs, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
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DEF_HELPER_FLAGS_4(gvec_xors, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
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DEF_HELPER_FLAGS_4(gvec_ors, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
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@ -330,6 +330,8 @@ void tcg_gen_gvec_ori(unsigned vece, uint32_t dofs, uint32_t aofs,
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void tcg_gen_gvec_ands(unsigned vece, uint32_t dofs, uint32_t aofs,
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TCGv_i64 c, uint32_t oprsz, uint32_t maxsz);
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void tcg_gen_gvec_andcs(unsigned vece, uint32_t dofs, uint32_t aofs,
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TCGv_i64 c, uint32_t oprsz, uint32_t maxsz);
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void tcg_gen_gvec_xors(unsigned vece, uint32_t dofs, uint32_t aofs,
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TCGv_i64 c, uint32_t oprsz, uint32_t maxsz);
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void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs,
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@ -2761,6 +2761,23 @@ void tcg_gen_gvec_andi(unsigned vece, uint32_t dofs, uint32_t aofs,
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tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ands);
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}
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void tcg_gen_gvec_andcs(unsigned vece, uint32_t dofs, uint32_t aofs,
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TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
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{
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static GVecGen2s g = {
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.fni8 = tcg_gen_andc_i64,
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.fniv = tcg_gen_andc_vec,
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.fno = gen_helper_gvec_andcs,
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.prefer_i64 = TCG_TARGET_REG_BITS == 64,
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.vece = MO_64
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};
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TCGv_i64 tmp = tcg_temp_ebb_new_i64();
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tcg_gen_dup_i64(vece, tmp, c);
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tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g);
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tcg_temp_free_i64(tmp);
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}
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static const GVecGen2s gop_xors = {
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.fni8 = tcg_gen_xor_i64,
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.fniv = tcg_gen_xor_vec,
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