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target/microblaze: Tidy raising of exceptions
Split out gen_raise_exception which does no cpu state sync. Rename t_gen_raise_exception to gen_raise_exception_sync to emphasize that it does a sync. Create gen_raise_hw_excp to simplify code raising EXCP_HW_EXCP. Since there is now only one use of cpu_esr, perform a store instead and remove the TCG variable. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -57,7 +57,6 @@ static TCGv_i32 env_debug;
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static TCGv_i32 cpu_R[32];
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static TCGv_i32 cpu_pc;
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static TCGv_i32 cpu_msr;
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static TCGv_i32 cpu_esr;
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static TCGv_i32 env_imm;
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static TCGv_i32 env_btaken;
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static TCGv_i32 cpu_btarget;
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@ -114,17 +113,31 @@ static inline void t_sync_flags(DisasContext *dc)
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}
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}
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static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
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static void gen_raise_exception(DisasContext *dc, uint32_t index)
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{
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TCGv_i32 tmp = tcg_const_i32(index);
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t_sync_flags(dc);
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tcg_gen_movi_i32(cpu_pc, dc->pc);
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gen_helper_raise_exception(cpu_env, tmp);
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tcg_temp_free_i32(tmp);
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dc->is_jmp = DISAS_UPDATE;
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}
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static void gen_raise_exception_sync(DisasContext *dc, uint32_t index)
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{
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t_sync_flags(dc);
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tcg_gen_movi_i32(cpu_pc, dc->pc);
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gen_raise_exception(dc, index);
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}
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static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec)
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{
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TCGv_i32 tmp = tcg_const_i32(esr_ec);
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tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, esr));
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tcg_temp_free_i32(tmp);
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gen_raise_exception_sync(dc, EXCP_HW_EXCP);
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}
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static inline bool use_goto_tb(DisasContext *dc, target_ulong dest)
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{
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#ifndef CONFIG_USER_ONLY
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@ -178,8 +191,7 @@ static bool trap_illegal(DisasContext *dc, bool cond)
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{
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if (cond && (dc->tb_flags & MSR_EE_FLAG)
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&& dc->cpu->cfg.illegal_opcode_exception) {
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tcg_gen_movi_i32(cpu_esr, ESR_EC_ILLEGAL_OP);
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t_gen_raise_exception(dc, EXCP_HW_EXCP);
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gen_raise_hw_excp(dc, ESR_EC_ILLEGAL_OP);
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}
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return cond;
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}
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@ -194,8 +206,7 @@ static bool trap_userspace(DisasContext *dc, bool cond)
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bool cond_user = cond && mem_index == MMU_USER_IDX;
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if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) {
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tcg_gen_movi_i32(cpu_esr, ESR_EC_PRIVINSN);
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t_gen_raise_exception(dc, EXCP_HW_EXCP);
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gen_raise_hw_excp(dc, ESR_EC_PRIVINSN);
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}
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return cond_user;
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}
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@ -540,7 +551,8 @@ static void dec_msr(DisasContext *dc)
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}
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break;
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case SR_ESR:
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tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]);
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tcg_gen_st_i32(cpu_R[dc->ra],
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cpu_env, offsetof(CPUMBState, esr));
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break;
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case SR_FSR:
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tcg_gen_st_i32(cpu_R[dc->ra],
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@ -589,7 +601,8 @@ static void dec_msr(DisasContext *dc)
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}
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break;
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case SR_ESR:
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tcg_gen_mov_i32(cpu_R[dc->rd], cpu_esr);
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tcg_gen_ld_i32(cpu_R[dc->rd],
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cpu_env, offsetof(CPUMBState, esr));
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break;
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case SR_FSR:
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tcg_gen_ld_i32(cpu_R[dc->rd],
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@ -1258,8 +1271,7 @@ static void dec_br(DisasContext *dc)
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/* mbar IMM & 16 decodes to sleep. */
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if (mbar_imm & 16) {
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TCGv_i32 tmp_hlt = tcg_const_i32(EXCP_HLT);
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TCGv_i32 tmp_1 = tcg_const_i32(1);
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TCGv_i32 tmp_1;
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LOG_DIS("sleep\n");
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@ -1269,13 +1281,16 @@ static void dec_br(DisasContext *dc)
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}
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t_sync_flags(dc);
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tmp_1 = tcg_const_i32(1);
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tcg_gen_st_i32(tmp_1, cpu_env,
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-offsetof(MicroBlazeCPU, env)
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+offsetof(CPUState, halted));
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tcg_gen_movi_i32(cpu_pc, dc->pc + 4);
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gen_helper_raise_exception(cpu_env, tmp_hlt);
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tcg_temp_free_i32(tmp_hlt);
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tcg_temp_free_i32(tmp_1);
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tcg_gen_movi_i32(cpu_pc, dc->pc + 4);
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gen_raise_exception(dc, EXCP_HLT);
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return;
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}
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/* Break the TB. */
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@ -1300,14 +1315,15 @@ static void dec_br(DisasContext *dc)
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tcg_gen_movi_i32(env_btaken, 1);
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tcg_gen_mov_i32(cpu_btarget, *(dec_alu_op_b(dc)));
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if (link && !dslot) {
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if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18))
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t_gen_raise_exception(dc, EXCP_BREAK);
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if (!(dc->tb_flags & IMM_FLAG) &&
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(dc->imm == 8 || dc->imm == 0x18)) {
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gen_raise_exception_sync(dc, EXCP_BREAK);
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}
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if (dc->imm == 0) {
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if (trap_userspace(dc, true)) {
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return;
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}
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t_gen_raise_exception(dc, EXCP_DEBUG);
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gen_raise_exception_sync(dc, EXCP_DEBUG);
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}
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}
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} else {
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@ -1411,8 +1427,7 @@ static void dec_rts(DisasContext *dc)
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static int dec_check_fpuv2(DisasContext *dc)
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{
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if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) {
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tcg_gen_movi_i32(cpu_esr, ESR_EC_FPU);
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t_gen_raise_exception(dc, EXCP_HW_EXCP);
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gen_raise_hw_excp(dc, ESR_EC_FPU);
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}
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return (dc->cpu->cfg.use_fpu == 2) ? PVR2_USE_FPU2_MASK : 0;
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}
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@ -1668,8 +1683,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
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#endif
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if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
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t_gen_raise_exception(dc, EXCP_DEBUG);
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dc->is_jmp = DISAS_UPDATE;
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gen_raise_exception_sync(dc, EXCP_DEBUG);
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/* The address covered by the breakpoint must be included in
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[tb->pc, tb->pc + tb->size) in order to for it to be
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properly cleared -- thus we increment the PC here so that
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@ -1874,8 +1888,6 @@ void mb_tcg_init(void)
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tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc");
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cpu_msr =
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tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, msr), "rmsr");
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cpu_esr =
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tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr");
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}
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void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb,
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