mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-09-06 18:05:37 +00:00
target/riscv: Remove the hardcoded SATP_MODE macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 6b701769d6621f45ba1739334198e36a64fe04df.1619234854.git.alistair.francis@wdc.com
This commit is contained in:
parent
4fd7455bb3
commit
419ddf00ed
|
@ -432,17 +432,6 @@
|
|||
#define SATP64_ASID 0x0FFFF00000000000ULL
|
||||
#define SATP64_PPN 0x00000FFFFFFFFFFFULL
|
||||
|
||||
#if defined(TARGET_RISCV32)
|
||||
#define SATP_MODE SATP32_MODE
|
||||
#define SATP_ASID SATP32_ASID
|
||||
#define SATP_PPN SATP32_PPN
|
||||
#endif
|
||||
#if defined(TARGET_RISCV64)
|
||||
#define SATP_MODE SATP64_MODE
|
||||
#define SATP_ASID SATP64_ASID
|
||||
#define SATP_PPN SATP64_PPN
|
||||
#endif
|
||||
|
||||
/* VM modes (mstatus.vm) privileged ISA 1.9.1 */
|
||||
#define VM_1_09_MBARE 0
|
||||
#define VM_1_09_MBB 1
|
||||
|
|
|
@ -405,11 +405,21 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
|
|||
|
||||
if (first_stage == true) {
|
||||
if (use_background) {
|
||||
base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT;
|
||||
vm = get_field(env->vsatp, SATP_MODE);
|
||||
if (riscv_cpu_is_32bit(env)) {
|
||||
base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
|
||||
vm = get_field(env->vsatp, SATP32_MODE);
|
||||
} else {
|
||||
base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT;
|
||||
vm = get_field(env->vsatp, SATP64_MODE);
|
||||
}
|
||||
} else {
|
||||
base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
|
||||
vm = get_field(env->satp, SATP_MODE);
|
||||
if (riscv_cpu_is_32bit(env)) {
|
||||
base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
|
||||
vm = get_field(env->satp, SATP32_MODE);
|
||||
} else {
|
||||
base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
|
||||
vm = get_field(env->satp, SATP64_MODE);
|
||||
}
|
||||
}
|
||||
widened = 0;
|
||||
} else {
|
||||
|
@ -624,14 +634,20 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
|
|||
{
|
||||
CPUState *cs = env_cpu(env);
|
||||
int page_fault_exceptions, vm;
|
||||
uint64_t stap_mode;
|
||||
|
||||
if (riscv_cpu_is_32bit(env)) {
|
||||
stap_mode = SATP32_MODE;
|
||||
} else {
|
||||
stap_mode = SATP64_MODE;
|
||||
}
|
||||
|
||||
if (first_stage) {
|
||||
vm = get_field(env->satp, SATP_MODE);
|
||||
} else if (riscv_cpu_is_32bit(env)) {
|
||||
vm = get_field(env->hgatp, SATP32_MODE);
|
||||
vm = get_field(env->satp, stap_mode);
|
||||
} else {
|
||||
vm = get_field(env->hgatp, SATP64_MODE);
|
||||
vm = get_field(env->hgatp, stap_mode);
|
||||
}
|
||||
|
||||
page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
|
||||
|
||||
switch (access_type) {
|
||||
|
|
|
@ -997,16 +997,27 @@ static RISCVException read_satp(CPURISCVState *env, int csrno,
|
|||
static RISCVException write_satp(CPURISCVState *env, int csrno,
|
||||
target_ulong val)
|
||||
{
|
||||
int vm, mask, asid;
|
||||
|
||||
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
|
||||
return RISCV_EXCP_NONE;
|
||||
}
|
||||
if (validate_vm(env, get_field(val, SATP_MODE)) &&
|
||||
((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
|
||||
{
|
||||
|
||||
if (riscv_cpu_is_32bit(env)) {
|
||||
vm = validate_vm(env, get_field(val, SATP32_MODE));
|
||||
mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
|
||||
asid = (val ^ env->satp) & SATP32_ASID;
|
||||
} else {
|
||||
vm = validate_vm(env, get_field(val, SATP64_MODE));
|
||||
mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
|
||||
asid = (val ^ env->satp) & SATP64_ASID;
|
||||
}
|
||||
|
||||
if (vm && mask) {
|
||||
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
|
||||
return RISCV_EXCP_ILLEGAL_INST;
|
||||
} else {
|
||||
if ((val ^ env->satp) & SATP_ASID) {
|
||||
if (asid) {
|
||||
tlb_flush(env_cpu(env));
|
||||
}
|
||||
env->satp = val;
|
||||
|
|
|
@ -150,9 +150,14 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env)
|
|||
target_ulong last_size;
|
||||
int last_attr;
|
||||
|
||||
base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
|
||||
if (riscv_cpu_is_32bit(env)) {
|
||||
base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
|
||||
vm = get_field(env->satp, SATP32_MODE);
|
||||
} else {
|
||||
base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
|
||||
vm = get_field(env->satp, SATP64_MODE);
|
||||
}
|
||||
|
||||
vm = get_field(env->satp, SATP_MODE);
|
||||
switch (vm) {
|
||||
case VM_1_10_SV32:
|
||||
levels = 2;
|
||||
|
@ -215,9 +220,16 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
|
|||
return;
|
||||
}
|
||||
|
||||
if (!(env->satp & SATP_MODE)) {
|
||||
monitor_printf(mon, "No translation or protection\n");
|
||||
return;
|
||||
if (riscv_cpu_is_32bit(env)) {
|
||||
if (!(env->satp & SATP32_MODE)) {
|
||||
monitor_printf(mon, "No translation or protection\n");
|
||||
return;
|
||||
}
|
||||
} else {
|
||||
if (!(env->satp & SATP64_MODE)) {
|
||||
monitor_printf(mon, "No translation or protection\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
mem_info_svxx(mon, env);
|
||||
|
|
Loading…
Reference in a new issue