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target/i386: emulate 64-bit ring 0 for linux-user if LM feature is set
32-bit binaries can run on a long mode processor even if the kernel is 64-bit, of course, and this can have slightly different behavior; for example, SYSCALL is allowed on Intel processors. Allow reporting LM to programs running under user mode emulation, so that "-cpu" can be used with named CPU models even for qemu-i386 and even without disabling LM by hand. Fortunately, most of the runtime code in QEMU has to depend on HF_LMA_MASK or on HF_CS64_MASK (which is anyway false for qemu-i386's 32-bit code segment) rather than TARGET_X86_64, therefore all that is needed is an update of linux-user's ring 0 setup. Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1534 Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -47,7 +47,7 @@ static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
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}
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static uint64_t *idt_table;
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#ifdef TARGET_X86_64
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static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
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uint64_t addr, unsigned int sel)
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{
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@ -60,8 +60,10 @@ static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
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p[2] = tswap32(addr >> 32);
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p[3] = 0;
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}
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#ifdef TARGET_X86_64
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/* only dpl matters as we do only user space emulation */
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static void set_idt(int n, unsigned int dpl)
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static void set_idt(int n, unsigned int dpl, bool is64)
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{
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set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
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}
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@ -78,9 +80,13 @@ static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
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}
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/* only dpl matters as we do only user space emulation */
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static void set_idt(int n, unsigned int dpl)
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static void set_idt(int n, unsigned int dpl, bool is64)
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{
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set_gate(idt_table + n, 0, dpl, 0, 0);
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if (is64) {
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set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
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} else {
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set_gate(idt_table + n, 0, dpl, 0, 0);
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}
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}
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#endif
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@ -325,6 +331,9 @@ static void target_cpu_free(void *obj)
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void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
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{
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CPUState *cpu = env_cpu(env);
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bool is64 = (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) != 0;
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int i;
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OBJECT(cpu)->free = target_cpu_free;
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env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
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env->hflags |= HF_PE_MASK | HF_CPL_MASK;
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@ -332,15 +341,18 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
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env->cr[4] |= CR4_OSFXSR_MASK;
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env->hflags |= HF_OSFXSR_MASK;
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}
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#ifndef TARGET_ABI32
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/* enable 64 bit mode if possible */
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if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
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if (is64) {
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env->cr[4] |= CR4_PAE_MASK;
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env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
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env->hflags |= HF_LMA_MASK;
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}
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#ifndef TARGET_ABI32
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else {
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fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
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exit(EXIT_FAILURE);
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}
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env->cr[4] |= CR4_PAE_MASK;
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env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
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env->hflags |= HF_LMA_MASK;
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#endif
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/* flags setup : we activate the IRQs by default as in user mode */
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@ -379,27 +391,12 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
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PROT_READ|PROT_WRITE,
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MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
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idt_table = g2h_untagged(env->idt.base);
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set_idt(0, 0);
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set_idt(1, 0);
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set_idt(2, 0);
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set_idt(3, 3);
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set_idt(4, 3);
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set_idt(5, 0);
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set_idt(6, 0);
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set_idt(7, 0);
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set_idt(8, 0);
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set_idt(9, 0);
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set_idt(10, 0);
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set_idt(11, 0);
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set_idt(12, 0);
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set_idt(13, 0);
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set_idt(14, 0);
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set_idt(15, 0);
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set_idt(16, 0);
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set_idt(17, 0);
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set_idt(18, 0);
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set_idt(19, 0);
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set_idt(0x80, 3);
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for (i = 0; i < 20; i++) {
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set_idt(i, 0, is64);
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}
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set_idt(3, 3, is64);
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set_idt(4, 3, is64);
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set_idt(0x80, 3, is64);
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/* linux segment setup */
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{
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@ -666,7 +666,10 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
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* and therefore using the 32-bit ABI; the CPU itself might be 64-bit
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* but again the difference is only visible in kernel mode.
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*/
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#if defined CONFIG_USER_ONLY
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#if defined CONFIG_LINUX_USER
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#define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR)
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#elif defined CONFIG_USER_ONLY
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/* FIXME: Long mode not yet supported for i386 bsd-user */
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#define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR
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#else
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#define CPUID_EXT2_KERNEL_FEATURES 0
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@ -5539,7 +5542,15 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
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}
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#ifndef TARGET_X86_64
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if (w == FEAT_8000_0001_EDX) {
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r &= ~CPUID_EXT2_LM;
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/*
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* 32-bit TCG can emulate 64-bit compatibility mode. If there is no
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* way for userspace to get out of its 32-bit jail, we can leave
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* the LM bit set.
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*/
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uint32_t unavail = tcg_enabled()
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? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES
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: CPUID_EXT2_LM;
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r &= ~unavail;
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}
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#endif
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if (migratable_only) {
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@ -173,12 +173,14 @@ typedef struct DisasContext {
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#endif
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#if !defined(TARGET_X86_64)
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#define CODE64(S) false
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#define LMA(S) false
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#elif defined(CONFIG_USER_ONLY)
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#define CODE64(S) true
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#define LMA(S) true
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#else
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#define CODE64(S) (((S)->flags & HF_CS64_MASK) != 0)
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#endif
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#if defined(CONFIG_SOFTMMU) && !defined(TARGET_X86_64)
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#define LMA(S) false
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#else
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#define LMA(S) (((S)->flags & HF_LMA_MASK) != 0)
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#endif
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