system/qemu
system/qemu
1
0
Fork 0
mirror of https://gitlab.com/qemu-project/qemu synced 2024-11-05 20:35:44 +00:00
Code Issues Projects Releases Packages Wiki Activity

target-tricore: Fix bugs found by coverity

Browse source 
This fixes one bug and one false positive found by coverity. The bug is,
that gen_mtcr was missing a mask to check the flag, which resulted in dead code.

The false positive is a intentional missing break for a jump and link address
insn followed by a jump and link insn. This adds a fall through comment to avoid
the false positive in the future.

Reported-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2015-01-21 16:16:01 +00:00
parent 811ea608e9
commit 40a1f64b46
2 changed files with 3 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
target-tricore/cpu.h
View file

@ -238,6 +238,7 @@ struct CPUTriCoreState {
#define MASK_LCX_LCXS 0x000f0000
#define MASK_LCX_LCX0 0x0000ffff
#define TRICORE_HFLAG_KUU 0x3
#define TRICORE_HFLAG_UM0 0x00002 /* user mode-0 flag */
#define TRICORE_HFLAG_UM1 0x00001 /* user mode-1 flag */
#define TRICORE_HFLAG_SM 0x00000 /* kernel mode flag */

3
target-tricore/translate.c
View file

@ -343,7 +343,7 @@ static inline void gen_mfcr(CPUTriCoreState *env, TCGv ret, int32_t offset)
static inline void gen_mtcr(CPUTriCoreState *env, DisasContext *ctx, TCGv r1,
int32_t offset)
{
if (ctx->hflags & TRICORE_HFLAG_SM) {
if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
/* since we're caching PSW make this a special case */
if (offset == 0xfe04) {
gen_helper_psw_write(cpu_env, r1);
@ -1647,6 +1647,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
break;
case OPC1_32_B_JLA:
tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
/* fall through */
case OPC1_32_B_JA:
gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
break;