mirror of
https://gitlab.com/qemu-project/qemu
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trivial patches for 2023-10-12
-----BEGIN PGP SIGNATURE----- iQFDBAABCAAtFiEEe3O61ovnosKJMUsicBtPaxppPlkFAmUnFa8PHG1qdEB0bHMu bXNrLnJ1AAoJEHAbT2saaT5ZBv8H/0MtWL6FqTzvz5yLn2WSbj2ng1RG1Deh36Sy 1PCpFKy85ZSBKLOzgvbpn4VfpEdsvD/+sX4C4CVde+vR3oCjdUM14hnzEWX86gFl O8Ct8++MLPqnwgu6Rg6Z+Ie2yBtsQ5VABH/1q36T7+XHHh19bgEw6tW34/f2Ncxw 8UQO2lm9tAMAOEfXoutoj8K8ch3FvbsEic9L0ORc7ntWc7NIauc3zizogtPHAzR8 elB3BiLn4sMHLBj+IunndOiLadUAVOKTJ5PKi4b8iRa6aE8E6bjtLxdiPr4XEx/g 7rSGvNM+Lm7mEgJSyyik+u0MshKjfRi+SrbvId9FIqACG1GCKeI= =rFns -----END PGP SIGNATURE----- Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging trivial patches for 2023-10-12 # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEe3O61ovnosKJMUsicBtPaxppPlkFAmUnFa8PHG1qdEB0bHMu # bXNrLnJ1AAoJEHAbT2saaT5ZBv8H/0MtWL6FqTzvz5yLn2WSbj2ng1RG1Deh36Sy # 1PCpFKy85ZSBKLOzgvbpn4VfpEdsvD/+sX4C4CVde+vR3oCjdUM14hnzEWX86gFl # O8Ct8++MLPqnwgu6Rg6Z+Ie2yBtsQ5VABH/1q36T7+XHHh19bgEw6tW34/f2Ncxw # 8UQO2lm9tAMAOEfXoutoj8K8ch3FvbsEic9L0ORc7ntWc7NIauc3zizogtPHAzR8 # elB3BiLn4sMHLBj+IunndOiLadUAVOKTJ5PKi4b8iRa6aE8E6bjtLxdiPr4XEx/g # 7rSGvNM+Lm7mEgJSyyik+u0MshKjfRi+SrbvId9FIqACG1GCKeI= # =rFns # -----END PGP SIGNATURE----- # gpg: Signature made Wed 11 Oct 2023 17:37:51 EDT # gpg: using RSA key 7B73BAD68BE7A2C289314B22701B4F6B1A693E59 # gpg: issuer "mjt@tls.msk.ru" # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" [full] # gpg: aka "Michael Tokarev <mjt@corpit.ru>" [full] # gpg: aka "Michael Tokarev <mjt@debian.org>" [full] # Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5 # Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931 4B22 701B 4F6B 1A69 3E59 * tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu: cpus: Remove unused smp_cores/smp_threads declarations scripts/xml-preprocess: Make sure this script is invoked via the right Python roms: use PYTHON to invoke python MAINTAINERS: Add some unowned files to the SBSA-REF section MAINTAINERS: Add section for overall sensors MAINTAINERS: add standard-headers to Hosts/LINUX MAINTAINERS: Add the CI-related doc files to the CI section MAINTAINERS: Add include folder to the hw/char/ section MAINTAINERS: Add unowned RISC-V related files to the right sections MAINTAINERS: Add g364fb and ds1225y to the Jazz section Fix compilation when UFFDIO_REGISTER is not set. Update AMD memory encryption document links. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
commit
40886c4cf5
24
MAINTAINERS
24
MAINTAINERS
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@ -318,8 +318,11 @@ R: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
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R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
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L: qemu-riscv@nongnu.org
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S: Supported
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F: configs/targets/riscv*
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F: docs/system/target-riscv.rst
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F: target/riscv/
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F: hw/riscv/
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F: hw/intc/riscv*
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F: include/hw/riscv/
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F: linux-user/host/riscv32/
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F: linux-user/host/riscv64/
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@ -331,6 +334,7 @@ L: qemu-riscv@nongnu.org
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S: Supported
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F: target/riscv/insn_trans/trans_xthead.c.inc
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F: target/riscv/xthead*.decode
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F: disas/riscv-xthead*
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RISC-V XVentanaCondOps extension
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M: Philipp Tomsich <philipp.tomsich@vrull.eu>
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@ -338,6 +342,7 @@ L: qemu-riscv@nongnu.org
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S: Maintained
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F: target/riscv/XVentanaCondOps.decode
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F: target/riscv/insn_trans/trans_xventanacondops.c.inc
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F: disas/riscv-xventana*
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RENESAS RX CPUs
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R: Yoshinori Sato <ysato@users.sourceforge.jp>
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@ -557,6 +562,7 @@ M: Cornelia Huck <cohuck@redhat.com>
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M: Paolo Bonzini <pbonzini@redhat.com>
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S: Maintained
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F: linux-headers/
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F: include/standard-headers/
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F: scripts/update-linux-headers.sh
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POSIX
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@ -939,6 +945,9 @@ R: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
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L: qemu-arm@nongnu.org
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S: Maintained
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F: hw/arm/sbsa-ref.c
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F: hw/misc/sbsa_ec.c
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F: hw/watchdog/sbsa_gwdt.c
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F: include/hw/watchdog/sbsa_gwdt.h
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F: docs/system/arm/sbsa.rst
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F: tests/avocado/machine_aarch64_sbsaref.py
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@ -1286,8 +1295,10 @@ M: Hervé Poussineau <hpoussin@reactos.org>
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R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
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S: Maintained
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F: hw/mips/jazz.c
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F: hw/display/g364fb.c
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F: hw/display/jazz_led.c
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F: hw/dma/rc4030.c
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F: hw/nvram/ds1225y.c
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Malta
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M: Philippe Mathieu-Daudé <philmd@linaro.org>
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@ -1525,6 +1536,7 @@ Microchip PolarFire SoC Icicle Kit
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M: Bin Meng <bin.meng@windriver.com>
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L: qemu-riscv@nongnu.org
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S: Supported
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F: docs/system/riscv/microchip-icicle-kit.rst
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F: hw/riscv/microchip_pfsoc.c
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F: hw/char/mchp_pfsoc_mmuart.c
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F: hw/misc/mchp_pfsoc_dmc.c
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@ -1540,6 +1552,7 @@ Shakti C class SoC
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M: Vijai Kumar K <vijai@behindbytes.com>
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L: qemu-riscv@nongnu.org
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S: Supported
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F: docs/system/riscv/shakti-c.rst
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F: hw/riscv/shakti_c.c
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F: hw/char/shakti_uart.c
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F: include/hw/riscv/shakti_c.h
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@ -1551,6 +1564,7 @@ M: Bin Meng <bin.meng@windriver.com>
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M: Palmer Dabbelt <palmer@dabbelt.com>
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L: qemu-riscv@nongnu.org
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S: Supported
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F: docs/system/riscv/sifive_u.rst
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F: hw/*/*sifive*.c
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F: include/hw/*/*sifive*.h
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@ -1978,6 +1992,7 @@ M: Marc-André Lureau <marcandre.lureau@redhat.com>
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R: Paolo Bonzini <pbonzini@redhat.com>
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S: Odd Fixes
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F: hw/char/
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F: include/hw/char/
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Network devices
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M: Jason Wang <jasowang@redhat.com>
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@ -3406,6 +3421,12 @@ M: Viktor Prutyanov <viktor.prutyanov@phystech.edu>
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S: Maintained
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F: contrib/elf2dmp/
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Overall sensors
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M: Philippe Mathieu-Daudé <philmd@linaro.org>
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S: Odd Fixes
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F: hw/sensor
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F: include/hw/sensor
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I2C and SMBus
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M: Corey Minyard <cminyard@mvista.com>
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S: Maintained
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@ -3571,7 +3592,7 @@ M: Alistair Francis <Alistair.Francis@wdc.com>
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L: qemu-riscv@nongnu.org
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S: Maintained
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F: tcg/riscv/
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F: disas/riscv.c
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F: disas/riscv.[ch]
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S390 TCG target
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M: Richard Henderson <richard.henderson@linaro.org>
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@ -3907,6 +3928,7 @@ F: .github/workflows/lockdown.yml
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F: .gitlab-ci.yml
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F: .gitlab-ci.d/
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F: .travis.yml
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F: docs/devel/ci*
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F: scripts/ci/
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F: tests/docker/
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F: tests/vm/
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@ -183,13 +183,13 @@ References
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----------
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`AMD Memory Encryption whitepaper
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<https://developer.amd.com/wordpress/media/2013/12/AMD_Memory_Encryption_Whitepaper_v7-Public.pdf>`_
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<https://www.amd.com/content/dam/amd/en/documents/epyc-business-docs/white-papers/memory-encryption-white-paper.pdf>`_
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.. [SEVAPI] `Secure Encrypted Virtualization API
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<https://www.amd.com/system/files/TechDocs/55766_SEV-KM_API_Specification.pdf>`_
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.. [APMVOL2] `AMD64 Architecture Programmer's Manual Volume 2: System Programming
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<https://www.amd.com/system/files/TechDocs/24593.pdf>`_
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<https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf>`_
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KVM Forum slides:
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@ -199,7 +199,7 @@ KVM Forum slides:
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<https://www.linux-kvm.org/images/9/94/Extending-Secure-Encrypted-Virtualization-with-SEV-ES-Thomas-Lendacky-AMD.pdf>`_
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`AMD64 Architecture Programmer's Manual:
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<http://support.amd.com/TechDocs/24593.pdf>`_
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<https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf>`_
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* SME is section 7.10
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* SEV is section 15.34
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@ -50,11 +50,4 @@ void cpu_synchronize_all_post_reset(void);
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void cpu_synchronize_all_post_init(void);
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void cpu_synchronize_all_pre_loadvm(void);
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#ifndef CONFIG_USER_ONLY
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/* vl.c */
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/* *-user doesn't have configurable SMP topology */
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extern int smp_cores;
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extern int smp_threads;
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#endif
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#endif
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@ -147,7 +147,7 @@ skiboot:
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cp skiboot/skiboot.lid ../pc-bios/skiboot.lid
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efi:
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python3 edk2-build.py --config edk2-build.config \
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$(PYTHON) edk2-build.py --config edk2-build.config \
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--version-override "edk2-stable202302-for-qemu" \
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--release-date "03/01/2023"
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rm -f ../pc-bios/edk2-*.fd.bz2
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0
scripts/xml-preprocess.py
Executable file → Normal file
0
scripts/xml-preprocess.py
Executable file → Normal file
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@ -631,9 +631,9 @@ static bool
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generate_faults(VuDev *dev) {
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unsigned int i;
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for (i = 0; i < dev->nregions; i++) {
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#ifdef UFFDIO_REGISTER
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VuDevRegion *dev_region = &dev->regions[i];
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int ret;
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#ifdef UFFDIO_REGISTER
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struct uffdio_register reg_struct;
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/*
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