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sifive_uart: Implement interrupt pending register
The watermark bits are set in the interrupt pending register according to the configuration of txcnt and rxcnt in the txctrl and rxctrl registers. Since the UART TX does not implement a FIFO, the txwm bit is set as long as the TX watermark level is greater than zero. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com> Reviewed-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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@ -28,12 +28,26 @@
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* Not yet implemented:
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*
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* Transmit FIFO using "qemu/fifo8.h"
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* SIFIVE_UART_IE_TXWM interrupts
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* SIFIVE_UART_IE_RXWM interrupts must honor fifo watermark
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* Rx FIFO watermark interrupt trigger threshold
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* Tx FIFO watermark interrupt trigger threshold.
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*/
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/* Returns the state of the IP (interrupt pending) register */
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static uint64_t uart_ip(SiFiveUARTState *s)
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{
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uint64_t ret = 0;
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uint64_t txcnt = SIFIVE_UART_GET_TXCNT(s->txctrl);
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uint64_t rxcnt = SIFIVE_UART_GET_RXCNT(s->rxctrl);
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if (txcnt != 0) {
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ret |= SIFIVE_UART_IP_TXWM;
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}
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if (s->rx_fifo_len > rxcnt) {
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ret |= SIFIVE_UART_IP_RXWM;
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}
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return ret;
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}
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static void update_irq(SiFiveUARTState *s)
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{
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int cond = 0;
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@ -69,7 +83,7 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
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case SIFIVE_UART_IE:
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return s->ie;
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case SIFIVE_UART_IP:
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return s->rx_fifo_len ? SIFIVE_UART_IP_RXWM : 0;
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return uart_ip(s);
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case SIFIVE_UART_TXCTRL:
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return s->txctrl;
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case SIFIVE_UART_RXCTRL:
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@ -43,6 +43,9 @@ enum {
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SIFIVE_UART_IP_RXWM = 2 /* Receive watermark interrupt pending */
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};
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#define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7)
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#define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7)
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#define TYPE_SIFIVE_UART "riscv.sifive.uart"
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#define SIFIVE_UART(obj) \
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