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target/microblaze: Fix width of MSR
The machine status register is only 32-bits wide. Do not use a 64-bit type to represent it. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -237,7 +237,7 @@ struct CPUMBState {
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uint32_t imm;
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uint32_t regs[32];
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uint32_t pc;
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uint64_t msr;
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uint32_t msr;
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uint64_t ear;
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uint64_t esr;
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uint64_t fsr;
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@ -222,7 +222,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
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}
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#endif
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qemu_log_mask(CPU_LOG_INT,
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"interrupt at pc=%x msr=%" PRIx64 " %x iflags=%x\n",
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"interrupt at pc=%x msr=%x %x iflags=%x\n",
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env->pc, env->msr, t, env->iflags);
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env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE);
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@ -239,7 +239,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
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assert(!(env->iflags & D_FLAG));
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t = (env->msr & (MSR_VM | MSR_UM)) << 1;
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qemu_log_mask(CPU_LOG_INT,
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"break at pc=%x msr=%" PRIx64 " %x iflags=%x\n",
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"break at pc=%x msr=%x %x iflags=%x\n",
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env->pc, env->msr, t, env->iflags);
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log_cpu_state_mask(CPU_LOG_INT, cs, 0);
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env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
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@ -76,7 +76,7 @@ void helper_debug(CPUMBState *env)
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int i;
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qemu_log("PC=%08x\n", env->pc);
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qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " "
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qemu_log("rmsr=%x resr=%" PRIx64 " rear=%" PRIx64 " "
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"debug[%x] imm=%x iflags=%x\n",
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env->msr, env->esr, env->ear,
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env->debug, env->imm, env->iflags);
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@ -56,7 +56,7 @@
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static TCGv_i32 env_debug;
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static TCGv_i32 cpu_R[32];
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static TCGv_i32 cpu_pc;
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static TCGv_i64 cpu_msr;
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static TCGv_i32 cpu_msr;
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static TCGv_i64 cpu_ear;
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static TCGv_i64 cpu_esr;
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static TCGv_i64 cpu_fsr;
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@ -152,8 +152,7 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
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static void read_carry(DisasContext *dc, TCGv_i32 d)
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{
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tcg_gen_extrl_i64_i32(d, cpu_msr);
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tcg_gen_shri_i32(d, d, 31);
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tcg_gen_shri_i32(d, cpu_msr, 31);
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}
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/*
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@ -162,12 +161,9 @@ static void read_carry(DisasContext *dc, TCGv_i32 d)
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*/
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static void write_carry(DisasContext *dc, TCGv_i32 v)
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{
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TCGv_i64 t0 = tcg_temp_new_i64();
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tcg_gen_extu_i32_i64(t0, v);
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/* Deposit bit 0 into MSR_C and the alias MSR_CC. */
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tcg_gen_deposit_i64(cpu_msr, cpu_msr, t0, 2, 1);
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tcg_gen_deposit_i64(cpu_msr, cpu_msr, t0, 31, 1);
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tcg_temp_free_i64(t0);
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tcg_gen_deposit_i32(cpu_msr, cpu_msr, v, 2, 1);
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tcg_gen_deposit_i32(cpu_msr, cpu_msr, v, 31, 1);
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}
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static void write_carryi(DisasContext *dc, bool carry)
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@ -437,21 +433,14 @@ static void dec_xor(DisasContext *dc)
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static inline void msr_read(DisasContext *dc, TCGv_i32 d)
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{
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tcg_gen_extrl_i64_i32(d, cpu_msr);
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tcg_gen_mov_i32(d, cpu_msr);
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}
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static inline void msr_write(DisasContext *dc, TCGv_i32 v)
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{
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TCGv_i64 t;
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t = tcg_temp_new_i64();
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dc->cpustate_changed = 1;
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/* PVR bit is not writable. */
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tcg_gen_extu_i32_i64(t, v);
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tcg_gen_andi_i64(t, t, ~MSR_PVR);
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tcg_gen_andi_i64(cpu_msr, cpu_msr, MSR_PVR);
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tcg_gen_or_i64(cpu_msr, cpu_msr, t);
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tcg_temp_free_i64(t);
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/* PVR bit is not writable, and is never set. */
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tcg_gen_andi_i32(cpu_msr, v, ~MSR_PVR);
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}
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static void dec_msr(DisasContext *dc)
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@ -773,8 +762,7 @@ static void dec_bit(DisasContext *dc)
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t0 = tcg_temp_new_i32();
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LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
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tcg_gen_extrl_i64_i32(t0, cpu_msr);
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tcg_gen_andi_i32(t0, t0, MSR_CC);
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tcg_gen_andi_i32(t0, cpu_msr, MSR_CC);
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write_carry(dc, cpu_R[dc->ra]);
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if (dc->rd) {
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tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1);
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@ -1326,7 +1314,7 @@ static inline void do_rti(DisasContext *dc)
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TCGv_i32 t0, t1;
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t0 = tcg_temp_new_i32();
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t1 = tcg_temp_new_i32();
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tcg_gen_extrl_i64_i32(t1, cpu_msr);
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tcg_gen_mov_i32(t1, cpu_msr);
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tcg_gen_shri_i32(t0, t1, 1);
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tcg_gen_ori_i32(t1, t1, MSR_IE);
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tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM));
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@ -1344,7 +1332,7 @@ static inline void do_rtb(DisasContext *dc)
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TCGv_i32 t0, t1;
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t0 = tcg_temp_new_i32();
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t1 = tcg_temp_new_i32();
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tcg_gen_extrl_i64_i32(t1, cpu_msr);
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tcg_gen_mov_i32(t1, cpu_msr);
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tcg_gen_andi_i32(t1, t1, ~MSR_BIP);
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tcg_gen_shri_i32(t0, t1, 1);
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tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM));
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@ -1363,7 +1351,7 @@ static inline void do_rte(DisasContext *dc)
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t0 = tcg_temp_new_i32();
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t1 = tcg_temp_new_i32();
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tcg_gen_extrl_i64_i32(t1, cpu_msr);
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tcg_gen_mov_i32(t1, cpu_msr);
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tcg_gen_ori_i32(t1, t1, MSR_EE);
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tcg_gen_andi_i32(t1, t1, ~MSR_EIP);
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tcg_gen_shri_i32(t0, t1, 1);
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@ -1809,7 +1797,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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qemu_fprintf(f, "IN: PC=%x %s\n",
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env->pc, lookup_symbol(env->pc));
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qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " "
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qemu_fprintf(f, "rmsr=%x resr=%" PRIx64 " rear=%" PRIx64 " "
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"debug=%x imm=%x iflags=%x fsr=%" PRIx64 " "
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"rbtr=%" PRIx64 "\n",
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env->msr, env->esr, env->ear,
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@ -1874,7 +1862,7 @@ void mb_tcg_init(void)
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cpu_pc =
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tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc");
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cpu_msr =
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tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr");
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tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, msr), "rmsr");
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cpu_ear =
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tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear");
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cpu_esr =
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