1
0
mirror of https://gitlab.com/qemu-project/qemu synced 2024-07-08 20:17:27 +00:00

accel/tcg: Move CPUNegativeOffsetState into CPUState

Retain the separate structure to emphasize its importance.
Enforce CPUArchState always follows CPUState without padding.

Reviewed-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-09-12 17:47:56 -07:00
parent 5d30bdcb1b
commit 3b3d7df545
25 changed files with 38 additions and 46 deletions

View File

@ -344,8 +344,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tcg_ctx->page_bits = TARGET_PAGE_BITS;
tcg_ctx->page_mask = TARGET_PAGE_MASK;
tcg_ctx->tlb_dyn_max_bits = CPU_TLB_DYN_MAX_BITS;
tcg_ctx->tlb_fast_offset =
(int)offsetof(ArchCPU, neg.tlb.f) - (int)offsetof(ArchCPU, env);
tcg_ctx->tlb_fast_offset = (int)offsetof(ArchCPU, parent_obj.neg.tlb.f)
- (int)offsetof(ArchCPU, env);
#endif
tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS;
#ifdef TCG_GUEST_DEFAULT_MO

View File

@ -48,8 +48,8 @@ static TCGOp *gen_tb_start(DisasContextBase *db, uint32_t cflags)
if ((cflags & CF_USE_ICOUNT) || !(cflags & CF_NOIRQ)) {
count = tcg_temp_new_i32();
tcg_gen_ld_i32(count, cpu_env,
offsetof(ArchCPU, neg.icount_decr.u32) -
offsetof(ArchCPU, env));
offsetof(ArchCPU, parent_obj.neg.icount_decr.u32)
- offsetof(ArchCPU, env));
}
if (cflags & CF_USE_ICOUNT) {
@ -78,8 +78,8 @@ static TCGOp *gen_tb_start(DisasContextBase *db, uint32_t cflags)
if (cflags & CF_USE_ICOUNT) {
tcg_gen_st16_i32(count, cpu_env,
offsetof(ArchCPU, neg.icount_decr.u16.low) -
offsetof(ArchCPU, env));
offsetof(ArchCPU, parent_obj.neg.icount_decr.u16.low)
- offsetof(ArchCPU, env));
}
/*

View File

@ -432,9 +432,13 @@ int cpu_exec(CPUState *cpu);
static inline void cpu_set_cpustate_pointers(ArchCPU *cpu)
{
cpu->parent_obj.env_ptr = &cpu->env;
cpu->parent_obj.icount_decr_ptr = &cpu->neg.icount_decr;
cpu->parent_obj.icount_decr_ptr = &cpu->parent_obj.neg.icount_decr;
}
/* Validate correct placement of CPUArchState. */
QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) != 0);
QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState));
/**
* env_archcpu(env)
* @env: The architecture environment
@ -443,7 +447,7 @@ static inline void cpu_set_cpustate_pointers(ArchCPU *cpu)
*/
static inline ArchCPU *env_archcpu(CPUArchState *env)
{
return container_of(env, ArchCPU, env);
return (void *)env - sizeof(CPUState);
}
/**
@ -454,15 +458,9 @@ static inline ArchCPU *env_archcpu(CPUArchState *env)
*/
static inline CPUState *env_cpu(CPUArchState *env)
{
return &env_archcpu(env)->parent_obj;
return (void *)env - sizeof(CPUState);
}
/*
* Validate placement of CPUNegativeOffsetState.
*/
QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) - offsetof(ArchCPU, neg) >=
sizeof(CPUNegativeOffsetState) + __alignof(CPUArchState));
/**
* env_neg(env)
* @env: The architecture environment
@ -471,8 +469,7 @@ QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) - offsetof(ArchCPU, neg) >=
*/
static inline CPUNegativeOffsetState *env_neg(CPUArchState *env)
{
ArchCPU *arch_cpu = container_of(env, ArchCPU, env);
return &arch_cpu->neg;
return &env_cpu(env)->neg;
}
/**
@ -483,8 +480,7 @@ static inline CPUNegativeOffsetState *env_neg(CPUArchState *env)
*/
static inline CPUNegativeOffsetState *cpu_neg(CPUState *cpu)
{
ArchCPU *arch_cpu = container_of(cpu, ArchCPU, parent_obj);
return &arch_cpu->neg;
return &cpu->neg;
}
/**

View File

@ -345,8 +345,8 @@ typedef union IcountDecr {
} IcountDecr;
/*
* This structure must be placed in ArchCPU immediately
* before CPUArchState, as a field named "neg".
* Elements of CPUState most efficiently accessed from CPUArchState,
* via small negative offsets.
*/
typedef struct CPUNegativeOffsetState {
CPUTLB tlb;
@ -453,6 +453,9 @@ struct qemu_work_item;
* dirty ring structure.
*
* State of one CPU core or thread.
*
* Align, in order to match possible alignment required by CPUArchState,
* and eliminate a hole between CPUState and CPUArchState within ArchCPU.
*/
struct CPUState {
/*< private >*/
@ -571,8 +574,18 @@ struct CPUState {
/* track IOMMUs whose translations we've cached in the TCG TLB */
GArray *iommu_notifiers;
/*
* MUST BE LAST in order to minimize the displacement to CPUArchState.
*/
char neg_align[-sizeof(CPUNegativeOffsetState) % 16] QEMU_ALIGNED(16);
CPUNegativeOffsetState neg;
};
/* Validate placement of CPUNegativeOffsetState. */
QEMU_BUILD_BUG_ON(offsetof(CPUState, neg) !=
sizeof(CPUState) - sizeof(CPUNegativeOffsetState));
typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ;
extern CPUTailQ cpus;

View File

@ -263,7 +263,6 @@ struct ArchCPU {
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPUAlphaState env;
/* This alarm doesn't exist in real hardware; we wish it did. */

View File

@ -856,7 +856,6 @@ struct ArchCPU {
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPUARMState env;
/* Coprocessor information */

View File

@ -148,7 +148,6 @@ struct ArchCPU {
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPUAVRState env;
};

View File

@ -178,7 +178,6 @@ struct ArchCPU {
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPUCRISState env;
};

View File

@ -141,7 +141,7 @@ struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPUHexagonState env;
bool lldb_compat;

View File

@ -237,7 +237,6 @@ struct ArchCPU {
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPUHPPAState env;
QEMUTimer *alarm_timer;
};

View File

@ -1901,7 +1901,6 @@ struct ArchCPU {
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPUX86State env;
VMChangeStateEntry *vmsentry;

View File

@ -375,7 +375,6 @@ struct ArchCPU {
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPULoongArchState env;
QEMUTimer timer;
uint32_t phy_id;

View File

@ -168,7 +168,6 @@ struct ArchCPU {
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPUM68KState env;
};

View File

@ -345,15 +345,15 @@ typedef struct {
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUMBState env;
bool ns_axi_dp;
bool ns_axi_ip;
bool ns_axi_dc;
bool ns_axi_ic;
CPUNegativeOffsetState neg;
CPUMBState env;
MicroBlazeCPUConfig cfg;
};

View File

@ -1213,10 +1213,10 @@ struct ArchCPU {
CPUState parent_obj;
/*< public >*/
CPUMIPSState env;
Clock *clock;
Clock *count_div; /* Divider for CP0_Count clock */
CPUNegativeOffsetState neg;
CPUMIPSState env;
};

View File

@ -218,7 +218,6 @@ struct ArchCPU {
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPUNios2State env;
bool diverr_present;

View File

@ -305,7 +305,6 @@ struct ArchCPU {
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPUOpenRISCState env;
};

View File

@ -1317,7 +1317,6 @@ struct ArchCPU {
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPUPPCState env;
int vcpu_id;

View File

@ -388,7 +388,7 @@ struct ArchCPU {
/* < private > */
CPUState parent_obj;
/* < public > */
CPUNegativeOffsetState neg;
CPURISCVState env;
char *dyn_csr_xml;

View File

@ -111,7 +111,6 @@ struct ArchCPU {
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPURXState env;
};

View File

@ -170,7 +170,6 @@ struct ArchCPU {
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPUS390XState env;
S390CPUModel *model;
/* needed for live migration */

View File

@ -208,7 +208,6 @@ struct ArchCPU {
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPUSH4State env;
};

View File

@ -561,7 +561,6 @@ struct ArchCPU {
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPUSPARCState env;
};

View File

@ -67,7 +67,6 @@ struct ArchCPU {
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPUTriCoreState env;
};

View File

@ -560,9 +560,8 @@ struct ArchCPU {
CPUState parent_obj;
/*< public >*/
Clock *clock;
CPUNegativeOffsetState neg;
CPUXtensaState env;
Clock *clock;
};