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target-xtensa: update qemu-doc.texi
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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@ -110,6 +110,7 @@ For system emulation, the following hardware targets are supported:
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@item Syborg SVP base model (ARM Cortex-A8).
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@item AXIS-Devboard88 (CRISv32 ETRAX-FS).
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@item Petalogix Spartan 3aDSP1800 MMU ref design (MicroBlaze).
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@item Avnet LX60/LX110/LX200 boards (Xtensa)
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@end itemize
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@cindex supported user mode targets
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@ -1446,6 +1447,7 @@ differences are mentioned in the following sections.
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* Cris System emulator::
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* Microblaze System emulator::
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* SH4 System emulator::
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* Xtensa System emulator::
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@end menu
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@node PowerPC System emulator
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@ -2124,6 +2126,59 @@ TODO
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TODO
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@node Xtensa System emulator
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@section Xtensa System emulator
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@cindex system emulation (Xtensa)
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Two executables cover simulation of both Xtensa endian options,
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@file{qemu-system-xtensa} and @file{qemu-system-xtensaeb}.
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Two different machine types are emulated:
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@itemize @minus
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@item
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Xtensa emulator pseudo board "sim"
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@item
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Avnet LX60/LX110/LX200 board
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@end itemize
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The sim pseudo board emulation provides an environment similiar
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to one provided by the proprietary Tensilica ISS.
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It supports:
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@itemize @minus
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@item
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A range of Xtensa CPUs, default is the DC232B
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@item
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Console and filesystem access via semihosting calls
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@end itemize
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The Avnet LX60/LX110/LX200 emulation supports:
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@itemize @minus
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@item
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A range of Xtensa CPUs, default is the DC232B
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@item
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16550 UART
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@item
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OpenCores 10/100 Mbps Ethernet MAC
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@end itemize
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@c man begin OPTIONS
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The following options are specific to the Xtensa emulation:
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@table @option
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@item -semihosting
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Enable semihosting syscall emulation.
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Xtensa semihosting provides basic file IO calls, such as open/read/write/seek/select.
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Tensilica baremetal libc for ISS and linux platform "sim" use this interface.
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Note that this allows guest direct access to the host filesystem,
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so should only be used with trusted guest OS.
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@end table
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@node QEMU User space emulator
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@chapter QEMU User space emulator
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@ -42,13 +42,14 @@
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@chapter Introduction
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@menu
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* intro_features:: Features
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* intro_x86_emulation:: x86 and x86-64 emulation
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* intro_arm_emulation:: ARM emulation
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* intro_mips_emulation:: MIPS emulation
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* intro_ppc_emulation:: PowerPC emulation
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* intro_sparc_emulation:: Sparc32 and Sparc64 emulation
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* intro_other_emulation:: Other CPU emulation
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* intro_features:: Features
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* intro_x86_emulation:: x86 and x86-64 emulation
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* intro_arm_emulation:: ARM emulation
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* intro_mips_emulation:: MIPS emulation
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* intro_ppc_emulation:: PowerPC emulation
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* intro_sparc_emulation:: Sparc32 and Sparc64 emulation
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* intro_xtensa_emulation:: Xtensa emulation
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* intro_other_emulation:: Other CPU emulation
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@end menu
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@node intro_features
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@ -259,6 +260,31 @@ Current QEMU limitations:
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@end itemize
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@node intro_xtensa_emulation
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@section Xtensa emulation
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@itemize
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@item Core Xtensa ISA emulation, including most options: code density,
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loop, extended L32R, 16- and 32-bit multiplication, 32-bit division,
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MAC16, miscellaneous operations, boolean, multiprocessor synchronization,
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conditional store, exceptions, relocatable vectors, unaligned exception,
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interrupts (including high priority and timer), hardware alignment,
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region protection, region translation, MMU, windowed registers, thread
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pointer, processor ID.
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@item Not implemented options: FP coprocessor, coprocessor context,
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data/instruction cache (including cache prefetch and locking), XLMI,
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processor interface, debug. Also options not covered by the core ISA
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(e.g. FLIX, wide branches) are not implemented.
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@item Can run most Xtensa Linux binaries.
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@item New core configuration that requires no additional instructions
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may be created from overlay with minimal amount of hand-written code.
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@end itemize
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@node intro_other_emulation
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@section Other CPU emulation
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