mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-10-06 19:19:41 +00:00
tcg/sparc: Remove support for sparc32plus
Since 9b9c37c364, we have only supported sparc64 cpus.
Debian and Gentoo now only support 64-bit sparc64 userland,
so it is time to drop the 32-bit sparc64 userland: sparc32plus.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
5107fd3eff
commit
3a5f6805c7
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@ -22,6 +22,11 @@
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* THE SOFTWARE.
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*/
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/* We only support generating code for 64-bit mode. */
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#ifndef __arch64__
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#error "unsupported code generation mode"
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#endif
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#include "../tcg-pool.c.inc"
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#ifdef CONFIG_DEBUG_TCG
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@ -61,12 +66,6 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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};
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#endif
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#ifdef __arch64__
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# define SPARC64 1
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#else
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# define SPARC64 0
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#endif
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#define TCG_CT_CONST_S11 0x100
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#define TCG_CT_CONST_S13 0x200
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#define TCG_CT_CONST_ZERO 0x400
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@ -91,11 +90,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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* high bits of the %i and %l registers garbage at all times.
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*/
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#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
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#if SPARC64
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# define ALL_GENERAL_REGS64 ALL_GENERAL_REGS
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#else
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# define ALL_GENERAL_REGS64 MAKE_64BIT_MASK(0, 16)
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#endif
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#define ALL_QLDST_REGS (ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
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#define ALL_QLDST_REGS64 (ALL_GENERAL_REGS64 & ~SOFTMMU_RESERVE_REGS)
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@ -306,11 +301,7 @@ static bool check_fit_i32(int32_t val, unsigned int bits)
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}
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#define check_fit_tl check_fit_i64
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#if SPARC64
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# define check_fit_ptr check_fit_i64
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#else
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# define check_fit_ptr check_fit_i32
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#endif
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#define check_fit_ptr check_fit_i64
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static bool patch_reloc(tcg_insn_unit *src_rw, int type,
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intptr_t value, intptr_t addend)
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@ -573,11 +564,6 @@ static void tcg_out_sety(TCGContext *s, TCGReg rs)
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tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs));
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}
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static void tcg_out_rdy(TCGContext *s, TCGReg rd)
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{
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tcg_out32(s, RDY | INSN_RD(rd));
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}
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static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1,
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int32_t val2, int val2const, int uns)
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{
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@ -914,9 +900,7 @@ static void emit_extend(TCGContext *s, TCGReg r, int op)
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tcg_out_arithi(s, r, r, 16, SHIFT_SRL);
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break;
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case MO_32:
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if (SPARC64) {
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tcg_out_arith(s, r, r, 0, SHIFT_SRL);
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}
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tcg_out_arith(s, r, r, 0, SHIFT_SRL);
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break;
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case MO_64:
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break;
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@ -948,7 +932,6 @@ static void build_trampolines(TCGContext *s)
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};
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int i;
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TCGReg ra;
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for (i = 0; i < ARRAY_SIZE(qemu_ld_helpers); ++i) {
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if (qemu_ld_helpers[i] == NULL) {
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@ -961,16 +944,8 @@ static void build_trampolines(TCGContext *s)
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}
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qemu_ld_trampoline[i] = tcg_splitwx_to_rx(s->code_ptr);
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if (SPARC64 || TARGET_LONG_BITS == 32) {
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ra = TCG_REG_O3;
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} else {
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/* Install the high part of the address. */
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tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O2, 32, SHIFT_SRLX);
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ra = TCG_REG_O4;
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}
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/* Set the retaddr operand. */
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tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7);
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tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O3, TCG_REG_O7);
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/* Tail call. */
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tcg_out_jmpl_const(s, qemu_ld_helpers[i], true, true);
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/* delay slot -- set the env argument */
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@ -988,37 +963,10 @@ static void build_trampolines(TCGContext *s)
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}
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qemu_st_trampoline[i] = tcg_splitwx_to_rx(s->code_ptr);
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if (SPARC64) {
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emit_extend(s, TCG_REG_O2, i);
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ra = TCG_REG_O4;
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} else {
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ra = TCG_REG_O1;
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if (TARGET_LONG_BITS == 64) {
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/* Install the high part of the address. */
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tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX);
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ra += 2;
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} else {
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ra += 1;
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}
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if ((i & MO_SIZE) == MO_64) {
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/* Install the high part of the data. */
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tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX);
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ra += 2;
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} else {
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emit_extend(s, ra, i);
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ra += 1;
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}
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/* Skip the oi argument. */
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ra += 1;
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}
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emit_extend(s, TCG_REG_O2, i);
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/* Set the retaddr operand. */
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if (ra >= TCG_REG_O6) {
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tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_O7, TCG_REG_CALL_STACK,
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TCG_TARGET_CALL_STACK_OFFSET);
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} else {
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tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7);
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}
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tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O4, TCG_REG_O7);
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/* Tail call. */
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tcg_out_jmpl_const(s, qemu_st_helpers[i], true, true);
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@ -1047,11 +995,6 @@ static void build_trampolines(TCGContext *s)
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qemu_unalign_st_trampoline = tcg_splitwx_to_rx(s->code_ptr);
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}
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if (!SPARC64 && TARGET_LONG_BITS == 64) {
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/* Install the high part of the address. */
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tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O2, 32, SHIFT_SRLX);
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}
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/* Tail call. */
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tcg_out_jmpl_const(s, helper, true, true);
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/* delay slot -- set the env argument */
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@ -1182,7 +1125,7 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index,
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tcg_out_cmp(s, r0, r2, 0);
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/* If the guest address must be zero-extended, do so now. */
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if (SPARC64 && TARGET_LONG_BITS == 32) {
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if (TARGET_LONG_BITS == 32) {
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tcg_out_arithi(s, r0, addr, 0, SHIFT_SRL);
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return r0;
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}
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@ -1231,7 +1174,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
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#ifdef CONFIG_SOFTMMU
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unsigned memi = get_mmuidx(oi);
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TCGReg addrz, param;
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TCGReg addrz;
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const tcg_insn_unit *func;
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addrz = tcg_out_tlb_load(s, addr, memi, memop,
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@ -1251,12 +1194,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
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/* TLB Miss. */
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param = TCG_REG_O1;
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if (!SPARC64 && TARGET_LONG_BITS == 64) {
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/* Skip the high-part; we'll perform the extract in the trampoline. */
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param++;
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}
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tcg_out_mov(s, TCG_TYPE_REG, param++, addrz);
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tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_O1, addrz);
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/* We use the helpers to extend SB and SW data, leaving the case
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of SL needing explicit extending below. */
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@ -1268,30 +1206,13 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
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tcg_debug_assert(func != NULL);
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tcg_out_call_nodelay(s, func, false);
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/* delay slot */
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tcg_out_movi(s, TCG_TYPE_I32, param, oi);
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tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_O2, oi);
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/* Recall that all of the helpers return 64-bit results.
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Which complicates things for sparcv8plus. */
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if (SPARC64) {
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/* We let the helper sign-extend SB and SW, but leave SL for here. */
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if (is_64 && (memop & MO_SSIZE) == MO_SL) {
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tcg_out_arithi(s, data, TCG_REG_O0, 0, SHIFT_SRA);
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} else {
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tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0);
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}
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/* We let the helper sign-extend SB and SW, but leave SL for here. */
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if (is_64 && (memop & MO_SSIZE) == MO_SL) {
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tcg_out_arithi(s, data, TCG_REG_O0, 0, SHIFT_SRA);
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} else {
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if ((memop & MO_SIZE) == MO_64) {
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tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, 32, SHIFT_SLLX);
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tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O1, 0, SHIFT_SRL);
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tcg_out_arith(s, data, TCG_REG_O0, TCG_REG_O1, ARITH_OR);
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} else if (is_64) {
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/* Re-extend from 32-bit rather than reassembling when we
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know the high register must be an extension. */
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tcg_out_arithi(s, data, TCG_REG_O1, 0,
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memop & MO_SIGN ? SHIFT_SRA : SHIFT_SRL);
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} else {
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tcg_out_mov(s, TCG_TYPE_I32, data, TCG_REG_O1);
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}
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tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0);
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}
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*label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr));
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@ -1301,7 +1222,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
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unsigned s_bits = memop & MO_SIZE;
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unsigned t_bits;
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if (SPARC64 && TARGET_LONG_BITS == 32) {
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if (TARGET_LONG_BITS == 32) {
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tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL);
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addr = TCG_REG_T1;
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}
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@ -1337,10 +1258,9 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
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* operation in the delay slot, and failure need only invoke the
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* handler for SIGBUS.
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*/
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TCGReg arg_low = TCG_REG_O1 + (!SPARC64 && TARGET_LONG_BITS == 64);
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tcg_out_call_nodelay(s, qemu_unalign_ld_trampoline, false);
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/* delay slot -- move to low part of argument reg */
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tcg_out_mov_delay(s, arg_low, addr);
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tcg_out_mov_delay(s, TCG_REG_O1, addr);
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} else {
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/* Underalignment: load by pieces of minimum alignment. */
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int ld_opc, a_size, s_size, i;
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@ -1400,7 +1320,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr,
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#ifdef CONFIG_SOFTMMU
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unsigned memi = get_mmuidx(oi);
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TCGReg addrz, param;
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TCGReg addrz;
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const tcg_insn_unit *func;
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addrz = tcg_out_tlb_load(s, addr, memi, memop,
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@ -1418,23 +1338,14 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr,
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/* TLB Miss. */
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param = TCG_REG_O1;
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if (!SPARC64 && TARGET_LONG_BITS == 64) {
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/* Skip the high-part; we'll perform the extract in the trampoline. */
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param++;
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}
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tcg_out_mov(s, TCG_TYPE_REG, param++, addrz);
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if (!SPARC64 && (memop & MO_SIZE) == MO_64) {
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/* Skip the high-part; we'll perform the extract in the trampoline. */
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param++;
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}
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tcg_out_mov(s, TCG_TYPE_REG, param++, data);
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tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_O1, addrz);
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tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_O2, data);
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func = qemu_st_trampoline[memop & (MO_BSWAP | MO_SIZE)];
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tcg_debug_assert(func != NULL);
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tcg_out_call_nodelay(s, func, false);
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/* delay slot */
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tcg_out_movi(s, TCG_TYPE_I32, param, oi);
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tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_O3, oi);
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*label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr));
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#else
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@ -1443,7 +1354,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr,
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unsigned s_bits = memop & MO_SIZE;
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unsigned t_bits;
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if (SPARC64 && TARGET_LONG_BITS == 32) {
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if (TARGET_LONG_BITS == 32) {
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tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL);
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addr = TCG_REG_T1;
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}
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@ -1479,10 +1390,9 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr,
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* operation in the delay slot, and failure need only invoke the
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* handler for SIGBUS.
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*/
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TCGReg arg_low = TCG_REG_O1 + (!SPARC64 && TARGET_LONG_BITS == 64);
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tcg_out_call_nodelay(s, qemu_unalign_st_trampoline, false);
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/* delay slot -- move to low part of argument reg */
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tcg_out_mov_delay(s, arg_low, addr);
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tcg_out_mov_delay(s, TCG_REG_O1, addr);
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} else {
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/* Underalignment: store by pieces of minimum alignment. */
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int st_opc, a_size, s_size, i;
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@ -1719,14 +1629,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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case INDEX_op_muls2_i32:
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c = ARITH_SMUL;
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do_mul2:
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/* The 32-bit multiply insns produce a full 64-bit result. If the
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destination register can hold it, we can avoid the slower RDY. */
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/* The 32-bit multiply insns produce a full 64-bit result. */
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tcg_out_arithc(s, a0, a2, args[3], const_args[3], c);
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if (SPARC64 || a0 <= TCG_REG_O7) {
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tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX);
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} else {
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tcg_out_rdy(s, a1);
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}
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tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX);
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break;
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case INDEX_op_qemu_ld_i32:
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@ -1984,16 +1889,11 @@ static void tcg_target_init(TCGContext *s)
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use */
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}
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#if SPARC64
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# define ELF_HOST_MACHINE EM_SPARCV9
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#else
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# define ELF_HOST_MACHINE EM_SPARC32PLUS
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# define ELF_HOST_FLAGS EF_SPARC_32PLUS
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#endif
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#define ELF_HOST_MACHINE EM_SPARCV9
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typedef struct {
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DebugFrameHeader h;
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uint8_t fde_def_cfa[SPARC64 ? 4 : 2];
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uint8_t fde_def_cfa[4];
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uint8_t fde_win_save;
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uint8_t fde_ret_save[3];
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} DebugFrame;
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@ -2010,12 +1910,8 @@ static const DebugFrame debug_frame = {
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.h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
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.fde_def_cfa = {
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#if SPARC64
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12, 30, /* DW_CFA_def_cfa i6, 2047 */
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(2047 & 0x7f) | 0x80, (2047 >> 7)
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#else
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13, 30 /* DW_CFA_def_cfa_register i6 */
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#endif
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},
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.fde_win_save = 0x2d, /* DW_CFA_GNU_window_save */
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.fde_ret_save = { 9, 15, 31 }, /* DW_CFA_register o7, i7 */
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@ -25,8 +25,6 @@
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#ifndef SPARC_TCG_TARGET_H
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#define SPARC_TCG_TARGET_H
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#define TCG_TARGET_REG_BITS 64
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#define TCG_TARGET_INSN_UNIT_SIZE 4
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#define TCG_TARGET_TLB_DISPLACEMENT_BITS 32
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#define TCG_TARGET_NB_REGS 32
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@ -70,19 +68,10 @@ typedef enum {
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/* used for function call generation */
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#define TCG_REG_CALL_STACK TCG_REG_O6
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#ifdef __arch64__
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#define TCG_TARGET_STACK_BIAS 2047
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#define TCG_TARGET_STACK_ALIGN 16
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#define TCG_TARGET_CALL_STACK_OFFSET (128 + 6*8 + TCG_TARGET_STACK_BIAS)
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#else
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#define TCG_TARGET_STACK_BIAS 0
|
||||
#define TCG_TARGET_STACK_ALIGN 8
|
||||
#define TCG_TARGET_CALL_STACK_OFFSET (64 + 4 + 6*4)
|
||||
#endif
|
||||
|
||||
#ifdef __arch64__
|
||||
#define TCG_TARGET_EXTEND_ARGS 1
|
||||
#endif
|
||||
|
||||
#if defined(__VIS__) && __VIS__ >= 0x300
|
||||
#define use_vis3_instructions 1
|
||||
|
|
|
|||
75
tcg/tcg.c
75
tcg/tcg.c
|
|
@ -1487,39 +1487,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(__sparc__) && !defined(__arch64__) \
|
||||
&& !defined(CONFIG_TCG_INTERPRETER)
|
||||
/* We have 64-bit values in one register, but need to pass as two
|
||||
separate parameters. Split them. */
|
||||
int orig_typemask = typemask;
|
||||
int orig_nargs = nargs;
|
||||
TCGv_i64 retl, reth;
|
||||
TCGTemp *split_args[MAX_OPC_PARAM];
|
||||
|
||||
retl = NULL;
|
||||
reth = NULL;
|
||||
typemask = 0;
|
||||
for (i = real_args = 0; i < nargs; ++i) {
|
||||
int argtype = extract32(orig_typemask, (i + 1) * 3, 3);
|
||||
bool is_64bit = (argtype & ~1) == dh_typecode_i64;
|
||||
|
||||
if (is_64bit) {
|
||||
TCGv_i64 orig = temp_tcgv_i64(args[i]);
|
||||
TCGv_i32 h = tcg_temp_new_i32();
|
||||
TCGv_i32 l = tcg_temp_new_i32();
|
||||
tcg_gen_extr_i64_i32(l, h, orig);
|
||||
split_args[real_args++] = tcgv_i32_temp(h);
|
||||
typemask |= dh_typecode_i32 << (real_args * 3);
|
||||
split_args[real_args++] = tcgv_i32_temp(l);
|
||||
typemask |= dh_typecode_i32 << (real_args * 3);
|
||||
} else {
|
||||
split_args[real_args++] = args[i];
|
||||
typemask |= argtype << (real_args * 3);
|
||||
}
|
||||
}
|
||||
nargs = real_args;
|
||||
args = split_args;
|
||||
#elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
|
||||
#if defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
|
||||
for (i = 0; i < nargs; ++i) {
|
||||
int argtype = extract32(typemask, (i + 1) * 3, 3);
|
||||
bool is_32bit = (argtype & ~1) == dh_typecode_i32;
|
||||
|
|
@ -1542,22 +1510,6 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
|
|||
|
||||
pi = 0;
|
||||
if (ret != NULL) {
|
||||
#if defined(__sparc__) && !defined(__arch64__) \
|
||||
&& !defined(CONFIG_TCG_INTERPRETER)
|
||||
if ((typemask & 6) == dh_typecode_i64) {
|
||||
/* The 32-bit ABI is going to return the 64-bit value in
|
||||
the %o0/%o1 register pair. Prepare for this by using
|
||||
two return temporaries, and reassemble below. */
|
||||
retl = tcg_temp_new_i64();
|
||||
reth = tcg_temp_new_i64();
|
||||
op->args[pi++] = tcgv_i64_arg(reth);
|
||||
op->args[pi++] = tcgv_i64_arg(retl);
|
||||
nb_rets = 2;
|
||||
} else {
|
||||
op->args[pi++] = temp_arg(ret);
|
||||
nb_rets = 1;
|
||||
}
|
||||
#else
|
||||
if (TCG_TARGET_REG_BITS < 64 && (typemask & 6) == dh_typecode_i64) {
|
||||
#if HOST_BIG_ENDIAN
|
||||
op->args[pi++] = temp_arg(ret + 1);
|
||||
|
|
@ -1571,7 +1523,6 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
|
|||
op->args[pi++] = temp_arg(ret);
|
||||
nb_rets = 1;
|
||||
}
|
||||
#endif
|
||||
} else {
|
||||
nb_rets = 0;
|
||||
}
|
||||
|
|
@ -1634,29 +1585,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
|
|||
tcg_debug_assert(TCGOP_CALLI(op) == real_args);
|
||||
tcg_debug_assert(pi <= ARRAY_SIZE(op->args));
|
||||
|
||||
#if defined(__sparc__) && !defined(__arch64__) \
|
||||
&& !defined(CONFIG_TCG_INTERPRETER)
|
||||
/* Free all of the parts we allocated above. */
|
||||
for (i = real_args = 0; i < orig_nargs; ++i) {
|
||||
int argtype = extract32(orig_typemask, (i + 1) * 3, 3);
|
||||
bool is_64bit = (argtype & ~1) == dh_typecode_i64;
|
||||
|
||||
if (is_64bit) {
|
||||
tcg_temp_free_internal(args[real_args++]);
|
||||
tcg_temp_free_internal(args[real_args++]);
|
||||
} else {
|
||||
real_args++;
|
||||
}
|
||||
}
|
||||
if ((orig_typemask & 6) == dh_typecode_i64) {
|
||||
/* The 32-bit ABI returned two 32-bit pieces. Re-assemble them.
|
||||
Note that describing these as TCGv_i64 eliminates an unnecessary
|
||||
zero-extension that tcg_gen_concat_i32_i64 would create. */
|
||||
tcg_gen_concat32_i64(temp_tcgv_i64(ret), retl, reth);
|
||||
tcg_temp_free_i64(retl);
|
||||
tcg_temp_free_i64(reth);
|
||||
}
|
||||
#elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
|
||||
#if defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
|
||||
for (i = 0; i < nargs; ++i) {
|
||||
int argtype = extract32(typemask, (i + 1) * 3, 3);
|
||||
bool is_32bit = (argtype & ~1) == dh_typecode_i32;
|
||||
|
|
|
|||
Loading…
Reference in a new issue