mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-11-05 20:35:44 +00:00
target-arm: Prepare translation for AArch64 code
This patch adds all the prerequisites for AArch64 support that didn't fit into split up patches. It extends important bits in the core cpu headers to also take AArch64 mode into account. Add new ARM_TBFLAG_AARCH64_STATE translation buffer flag indicate an ARMv8 cpu running in aarch64 mode vs aarch32 mode. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-10-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-4-git-send-email-john.rigby@linaro.org [PMM: * rearranged tbflags so AArch64? is bit 31 and if it is set then 30..0 are freely available for whatever makes most sense for that mode * added version bump since we change VFP migration state * added a comment about how VFP/Neon register state works * physical address space is 48 bits, not 64 * added ARM_FEATURE_AARCH64 flag to identify 64-bit capable CPUs ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alexander Graf
Peter Maydell
parent
15ee776bf2
commit
3926cc8433
5 changed files with 151 additions and 38 deletions
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@ -84,6 +84,11 @@ static void arm_cpu_reset(CPUState *s)
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env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
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}
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if (arm_feature(env, ARM_FEATURE_AARCH64)) {
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/* 64 bit CPUs always start in 64 bit mode */
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env->aarch64 = 1;
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}
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#if defined(CONFIG_USER_ONLY)
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env->uncached_cpsr = ARM_CPU_MODE_USR;
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/* For user mode we must enable access to coprocessors */
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@ -834,6 +839,9 @@ static void arm_any_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
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set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
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set_feature(&cpu->env, ARM_FEATURE_V7MP);
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#ifdef TARGET_AARCH64
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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#endif
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cpu->midr = 0xffffffff;
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}
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#endif
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134
target-arm/cpu.h
134
target-arm/cpu.h
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@ -19,13 +19,19 @@
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#ifndef CPU_ARM_H
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#define CPU_ARM_H
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#define TARGET_LONG_BITS 32
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#include "config.h"
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#define ELF_MACHINE EM_ARM
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#if defined(TARGET_AARCH64)
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/* AArch64 definitions */
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# define TARGET_LONG_BITS 64
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# define ELF_MACHINE EM_AARCH64
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#else
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# define TARGET_LONG_BITS 32
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# define ELF_MACHINE EM_ARM
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#endif
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#define CPUArchState struct CPUARMState
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#include "config.h"
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#include "qemu-common.h"
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#include "exec/cpu-defs.h"
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@ -97,6 +103,20 @@ typedef struct ARMGenericTimer {
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typedef struct CPUARMState {
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/* Regs for current mode. */
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uint32_t regs[16];
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/* 32/64 switch only happens when taking and returning from
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* exceptions so the overlap semantics are taken care of then
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* instead of having a complicated union.
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*/
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/* Regs for A64 mode. */
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uint64_t xregs[32];
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uint64_t pc;
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/* TODO: pstate doesn't correspond to an architectural register;
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* it would be better modelled as the underlying fields.
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*/
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uint32_t pstate;
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uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
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/* Frequently accessed CPSR bits are stored separately for efficiency.
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This contains all the other bits. Use cpsr_{read,write} to access
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the whole CPSR. */
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@ -175,6 +195,11 @@ typedef struct CPUARMState {
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uint32_t c15_power_control; /* power control */
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} cp15;
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/* System registers (AArch64) */
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struct {
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uint64_t tpidr_el0;
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} sr;
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struct {
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uint32_t other_sp;
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uint32_t vecbase;
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@ -191,7 +216,22 @@ typedef struct CPUARMState {
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/* VFP coprocessor state. */
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struct {
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float64 regs[32];
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/* VFP/Neon register state. Note that the mapping between S, D and Q
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* views of the register bank differs between AArch64 and AArch32:
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* In AArch32:
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* Qn = regs[2n+1]:regs[2n]
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* Dn = regs[n]
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* Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n
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* (and regs[32] to regs[63] are inaccessible)
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* In AArch64:
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* Qn = regs[2n+1]:regs[2n]
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* Dn = regs[2n]
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* Sn = regs[2n] bits 31..0
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* This corresponds to the architecturally defined mapping between
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* the two execution states, and means we do not need to explicitly
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* map these registers when changing states.
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*/
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float64 regs[64];
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uint32_t xregs[16];
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/* We store these fpcsr fields separately for convenience. */
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@ -261,6 +301,20 @@ int bank_number(int mode);
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void switch_mode(CPUARMState *, int);
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uint32_t do_arm_semihosting(CPUARMState *env);
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static inline bool is_a64(CPUARMState *env)
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{
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return env->aarch64;
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}
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#define PSTATE_N_SHIFT 3
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#define PSTATE_N (1 << PSTATE_N_SHIFT)
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#define PSTATE_Z_SHIFT 2
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#define PSTATE_Z (1 << PSTATE_Z_SHIFT)
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#define PSTATE_C_SHIFT 1
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#define PSTATE_C (1 << PSTATE_C_SHIFT)
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#define PSTATE_V_SHIFT 0
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#define PSTATE_V (1 << PSTATE_V_SHIFT)
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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signal handlers to inform the virtual CPU of exceptions. non zero
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is returned if the signal was handled by the virtual CPU. */
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@ -409,6 +463,7 @@ enum arm_features {
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ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
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ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
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ARM_FEATURE_V8,
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ARM_FEATURE_AARCH64, /* supports 64 bit mode */
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};
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static inline int arm_feature(CPUARMState *env, int feature)
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@ -729,8 +784,13 @@ bool write_cpustate_to_list(ARMCPU *cpu);
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#define TARGET_PAGE_BITS 10
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#endif
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#define TARGET_PHYS_ADDR_SPACE_BITS 40
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#define TARGET_VIRT_ADDR_SPACE_BITS 32
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#if defined(TARGET_AARCH64)
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# define TARGET_PHYS_ADDR_SPACE_BITS 48
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# define TARGET_VIRT_ADDR_SPACE_BITS 64
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#else
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# define TARGET_PHYS_ADDR_SPACE_BITS 40
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# define TARGET_VIRT_ADDR_SPACE_BITS 32
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#endif
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static inline CPUARMState *cpu_init(const char *cpu_model)
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{
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@ -757,7 +817,13 @@ static inline int cpu_mmu_index (CPUARMState *env)
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#include "exec/cpu-all.h"
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/* Bit usage in the TB flags field: */
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/* Bit usage in the TB flags field: bit 31 indicates whether we are
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* in 32 or 64 bit mode. The meaning of the other bits depends on that.
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*/
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#define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
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#define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
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/* Bit usage when in AArch32 state: */
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#define ARM_TBFLAG_THUMB_SHIFT 0
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#define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
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#define ARM_TBFLAG_VECLEN_SHIFT 1
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@ -772,9 +838,12 @@ static inline int cpu_mmu_index (CPUARMState *env)
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#define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
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#define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
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#define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
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/* Bits 31..17 are currently unused. */
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/* Bit usage when in AArch64 state: currently no bits defined */
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/* some convenience accessor macros */
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#define ARM_TBFLAG_AARCH64_STATE(F) \
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(((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
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#define ARM_TBFLAG_THUMB(F) \
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(((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
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#define ARM_TBFLAG_VECLEN(F) \
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@ -793,25 +862,31 @@ static inline int cpu_mmu_index (CPUARMState *env)
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static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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target_ulong *cs_base, int *flags)
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{
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int privmode;
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*pc = env->regs[15];
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*cs_base = 0;
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*flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
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| (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
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| (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
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| (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
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| (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
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if (arm_feature(env, ARM_FEATURE_M)) {
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privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
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if (is_a64(env)) {
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*pc = env->pc;
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*flags = ARM_TBFLAG_AARCH64_STATE_MASK;
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} else {
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privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
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}
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if (privmode) {
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*flags |= ARM_TBFLAG_PRIV_MASK;
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}
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if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
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*flags |= ARM_TBFLAG_VFPEN_MASK;
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int privmode;
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*pc = env->regs[15];
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*flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
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| (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
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| (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
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| (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
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| (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
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if (arm_feature(env, ARM_FEATURE_M)) {
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privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
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} else {
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privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
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}
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if (privmode) {
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*flags |= ARM_TBFLAG_PRIV_MASK;
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}
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if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
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*flags |= ARM_TBFLAG_VFPEN_MASK;
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}
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}
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*cs_base = 0;
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}
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static inline bool cpu_has_work(CPUState *cpu)
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@ -822,6 +897,15 @@ static inline bool cpu_has_work(CPUState *cpu)
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#include "exec/exec-all.h"
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static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
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{
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if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
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env->pc = tb->pc;
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} else {
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env->regs[15] = tb->pc;
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}
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}
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/* Load an instruction and return it in the standard little-endian order */
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static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
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bool do_swap)
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@ -37,11 +37,11 @@ static const VMStateInfo vmstate_fpscr = {
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static const VMStateDescription vmstate_vfp = {
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.name = "cpu/vfp",
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.version_id = 2,
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.minimum_version_id = 2,
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.minimum_version_id_old = 2,
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.version_id = 3,
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.minimum_version_id = 3,
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.minimum_version_id_old = 3,
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.fields = (VMStateField[]) {
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VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 32),
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VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64),
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/* The xregs array is a little awkward because element 1 (FPSCR)
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* requires a specific accessor, so we have to split it up in
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* the vmstate:
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@ -10012,16 +10012,32 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
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dc->pc = pc_start;
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dc->singlestep_enabled = cs->singlestep_enabled;
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dc->condjmp = 0;
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dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
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dc->bswap_code = ARM_TBFLAG_BSWAP_CODE(tb->flags);
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dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
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dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
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if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
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dc->aarch64 = 1;
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dc->thumb = 0;
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dc->bswap_code = 0;
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dc->condexec_mask = 0;
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dc->condexec_cond = 0;
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#if !defined(CONFIG_USER_ONLY)
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dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0);
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dc->user = 0;
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#endif
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dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
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dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
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dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
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dc->vfp_enabled = 0;
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dc->vec_len = 0;
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dc->vec_stride = 0;
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} else {
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dc->aarch64 = 0;
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dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
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dc->bswap_code = ARM_TBFLAG_BSWAP_CODE(tb->flags);
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dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
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dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
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#if !defined(CONFIG_USER_ONLY)
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dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0);
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#endif
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dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
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dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
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dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
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}
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cpu_F0s = tcg_temp_new_i32();
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cpu_F1s = tcg_temp_new_i32();
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cpu_F0d = tcg_temp_new_i64();
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@ -10324,6 +10340,10 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
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void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb, int pc_pos)
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{
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env->regs[15] = tcg_ctx.gen_opc_pc[pc_pos];
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if (is_a64(env)) {
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env->pc = tcg_ctx.gen_opc_pc[pc_pos];
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} else {
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env->regs[15] = tcg_ctx.gen_opc_pc[pc_pos];
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}
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env->condexec_bits = gen_opc_condexec_bits[pc_pos];
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}
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@ -22,6 +22,7 @@ typedef struct DisasContext {
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int vfp_enabled;
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int vec_len;
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int vec_stride;
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int aarch64;
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} DisasContext;
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extern TCGv_ptr cpu_env;
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