system/qemu
system/qemu
1
0
Fork 0
mirror of https://gitlab.com/qemu-project/qemu synced 2024-10-14 15:02:54 +00:00
Code Issues Packages Projects Releases Wiki Activity

hw/cxl: Use switch statements for read and write of cachemem registers

Browse source 
Establishing that only register accesses of size 4 and 8 can occur
using these functions requires looking at their callers. Make it
easier to see that by using switch statements.
Assertions are used to enforce that the register storage is of the
matching size, allowing fixed values to be used for divisors of
the array indices.

Suggested-by: Michael Tokarev <mjt@tls.msk.ru>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>

Message-Id: <20231023140210.3089-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Jonathan Cameron 2023-10-23 15:02:07 +01:00 committed by Michael S. Tsirkin
parent 629df5cc23
commit 388d6b574e
1 changed files with 43 additions and 23 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

66
hw/cxl/cxl-component-utils.c
View file

@ -67,16 +67,24 @@ static uint64_t cxl_cache_mem_read_reg(void *opaque, hwaddr offset,
CXLComponentState *cxl_cstate = opaque; CXLComponentState *cxl_cstate = opaque;
ComponentRegisters *cregs = &cxl_cstate->crb; ComponentRegisters *cregs = &cxl_cstate->crb;
if (size == 8) { switch (size) {
case 4:
if (cregs->special_ops && cregs->special_ops->read) {
return cregs->special_ops->read(cxl_cstate, offset, 4);
} else {
QEMU_BUILD_BUG_ON(sizeof(*cregs->cache_mem_registers) != 4);
return cregs->cache_mem_registers[offset / 4];
}
case 8:
qemu_log_mask(LOG_UNIMP, qemu_log_mask(LOG_UNIMP,
"CXL 8 byte cache mem registers not implemented\n"); "CXL 8 byte cache mem registers not implemented\n");
return 0; return 0;
} default:
/*
if (cregs->special_ops && cregs->special_ops->read) { * In line with specifiction limitaions on access sizes, this
return cregs->special_ops->read(cxl_cstate, offset, size); * routine is not called with other sizes.
} else { */
return cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)]; g_assert_not_reached();
} }
} }
@ -117,25 +125,37 @@ static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t value,
ComponentRegisters *cregs = &cxl_cstate->crb; ComponentRegisters *cregs = &cxl_cstate->crb;
uint32_t mask; uint32_t mask;
if (size == 8) { switch (size) {
case 4: {
QEMU_BUILD_BUG_ON(sizeof(*cregs->cache_mem_regs_write_mask) != 4);
QEMU_BUILD_BUG_ON(sizeof(*cregs->cache_mem_registers) != 4);
mask = cregs->cache_mem_regs_write_mask[offset / 4];
value &= mask;
/* RO bits should remain constant. Done by reading existing value */
value |= ~mask & cregs->cache_mem_registers[offset / 4];
if (cregs->special_ops && cregs->special_ops->write) {
cregs->special_ops->write(cxl_cstate, offset, value, size);
return;
}
if (offset >= A_CXL_HDM_DECODER_CAPABILITY &&
offset <= A_CXL_HDM_DECODER3_TARGET_LIST_HI) {
dumb_hdm_handler(cxl_cstate, offset, value);
} else {
cregs->cache_mem_registers[offset / 4] = value;
}
return;
}
case 8:
qemu_log_mask(LOG_UNIMP, qemu_log_mask(LOG_UNIMP,
"CXL 8 byte cache mem registers not implemented\n"); "CXL 8 byte cache mem registers not implemented\n");
return; return;
} default:
mask = cregs->cache_mem_regs_write_mask[offset / sizeof(*cregs->cache_mem_regs_write_mask)]; /*
value &= mask; * In line with specifiction limitaions on access sizes, this
/* RO bits should remain constant. Done by reading existing value */ * routine is not called with other sizes.
value |= ~mask & cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)]; */
if (cregs->special_ops && cregs->special_ops->write) { g_assert_not_reached();
cregs->special_ops->write(cxl_cstate, offset, value, size);
return;
}
if (offset >= A_CXL_HDM_DECODER_CAPABILITY &&
offset <= A_CXL_HDM_DECODER3_TARGET_LIST_HI) {
dumb_hdm_handler(cxl_cstate, offset, value);
} else {
cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)] = value;
} }
} }