mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-11-05 20:35:44 +00:00
memory: dispatch directly via MemoryRegion
Instead of indirecting via io_mem_region, dispatch directly through the MemoryRegion obtained from the iotlb or phys_page_find(). Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Avi Kivity
parent
ce5d64c2d0
commit
37ec01d433
4 changed files with 73 additions and 102 deletions
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@ -299,10 +299,11 @@ extern void *tci_tb_ptr;
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#if !defined(CONFIG_USER_ONLY)
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target_phys_addr_t section_to_ioaddr(target_phys_addr_t section_io_addr);
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uint64_t io_mem_read(int index, target_phys_addr_t addr, unsigned size);
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void io_mem_write(int index, target_phys_addr_t addr, uint64_t value,
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unsigned size);
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struct MemoryRegion *iotlb_to_region(target_phys_addr_t index);
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uint64_t io_mem_read(struct MemoryRegion *mr, target_phys_addr_t addr,
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unsigned size);
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void io_mem_write(struct MemoryRegion *mr, target_phys_addr_t addr,
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uint64_t value, unsigned size);
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extern struct MemoryRegion *io_mem_region[IO_MEM_NB_ENTRIES];
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void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
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110
exec.c
110
exec.c
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@ -3399,7 +3399,7 @@ static uint64_t subpage_read(void *opaque, target_phys_addr_t addr,
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addr += mmio->base;
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addr -= section->offset_within_address_space;
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addr += section->offset_within_region;
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return io_mem_read(section->mr->ram_addr, addr, len);
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return io_mem_read(section->mr, addr, len);
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}
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static void subpage_write(void *opaque, target_phys_addr_t addr,
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@ -3418,7 +3418,7 @@ static void subpage_write(void *opaque, target_phys_addr_t addr,
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addr += mmio->base;
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addr -= section->offset_within_address_space;
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addr += section->offset_within_region;
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io_mem_write(section->mr->ram_addr, addr, value, len);
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io_mem_write(section->mr, addr, value, len);
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}
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static const MemoryRegionOps subpage_ops = {
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@ -3562,13 +3562,9 @@ static uint16_t dummy_section(MemoryRegion *mr)
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return phys_section_add(§ion);
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}
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target_phys_addr_t section_to_ioaddr(target_phys_addr_t section_io_addr)
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MemoryRegion *iotlb_to_region(target_phys_addr_t index)
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{
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MemoryRegionSection *section;
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section = &phys_sections[section_io_addr & ~TARGET_PAGE_MASK];
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return (section_io_addr & TARGET_PAGE_MASK)
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| (section->mr->ram_addr & ~TARGET_PAGE_MASK);
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return phys_sections[index & ~TARGET_PAGE_MASK].mr;
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}
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static void io_mem_init(void)
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@ -3838,7 +3834,7 @@ int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
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void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
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int len, int is_write)
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{
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int l, io_index;
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int l;
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uint8_t *ptr;
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uint32_t val;
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target_phys_addr_t page;
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@ -3854,25 +3850,23 @@ void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
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if (is_write) {
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if (!memory_region_is_ram(section->mr)) {
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target_phys_addr_t addr1;
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io_index = memory_region_get_ram_addr(section->mr)
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& (IO_MEM_NB_ENTRIES - 1);
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addr1 = section_addr(section, addr);
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/* XXX: could force cpu_single_env to NULL to avoid
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potential bugs */
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if (l >= 4 && ((addr1 & 3) == 0)) {
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/* 32 bit write access */
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val = ldl_p(buf);
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io_mem_write(io_index, addr1, val, 4);
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io_mem_write(section->mr, addr1, val, 4);
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l = 4;
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} else if (l >= 2 && ((addr1 & 1) == 0)) {
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/* 16 bit write access */
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val = lduw_p(buf);
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io_mem_write(io_index, addr1, val, 2);
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io_mem_write(section->mr, addr1, val, 2);
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l = 2;
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} else {
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/* 8 bit write access */
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val = ldub_p(buf);
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io_mem_write(io_index, addr1, val, 1);
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io_mem_write(section->mr, addr1, val, 1);
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l = 1;
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}
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} else if (!section->readonly) {
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@ -3895,22 +3889,20 @@ void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
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if (!is_ram_rom_romd(section)) {
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target_phys_addr_t addr1;
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/* I/O case */
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io_index = memory_region_get_ram_addr(section->mr)
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& (IO_MEM_NB_ENTRIES - 1);
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addr1 = section_addr(section, addr);
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if (l >= 4 && ((addr1 & 3) == 0)) {
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/* 32 bit read access */
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val = io_mem_read(io_index, addr1, 4);
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val = io_mem_read(section->mr, addr1, 4);
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stl_p(buf, val);
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l = 4;
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} else if (l >= 2 && ((addr1 & 1) == 0)) {
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/* 16 bit read access */
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val = io_mem_read(io_index, addr1, 2);
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val = io_mem_read(section->mr, addr1, 2);
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stw_p(buf, val);
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l = 2;
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} else {
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/* 8 bit read access */
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val = io_mem_read(io_index, addr1, 1);
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val = io_mem_read(section->mr, addr1, 1);
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stb_p(buf, val);
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l = 1;
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}
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@ -4106,7 +4098,6 @@ void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
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static inline uint32_t ldl_phys_internal(target_phys_addr_t addr,
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enum device_endian endian)
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{
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int io_index;
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uint8_t *ptr;
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uint32_t val;
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MemoryRegionSection *section;
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@ -4115,10 +4106,8 @@ static inline uint32_t ldl_phys_internal(target_phys_addr_t addr,
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if (!is_ram_rom_romd(section)) {
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/* I/O case */
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io_index = memory_region_get_ram_addr(section->mr)
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& (IO_MEM_NB_ENTRIES - 1);
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addr = section_addr(section, addr);
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val = io_mem_read(io_index, addr, 4);
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val = io_mem_read(section->mr, addr, 4);
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap32(val);
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@ -4167,7 +4156,6 @@ uint32_t ldl_be_phys(target_phys_addr_t addr)
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static inline uint64_t ldq_phys_internal(target_phys_addr_t addr,
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enum device_endian endian)
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{
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int io_index;
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uint8_t *ptr;
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uint64_t val;
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MemoryRegionSection *section;
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@ -4176,18 +4164,16 @@ static inline uint64_t ldq_phys_internal(target_phys_addr_t addr,
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if (!is_ram_rom_romd(section)) {
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/* I/O case */
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io_index = memory_region_get_ram_addr(section->mr)
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& (IO_MEM_NB_ENTRIES - 1);
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addr = section_addr(section, addr);
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/* XXX This is broken when device endian != cpu endian.
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Fix and add "endian" variable check */
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#ifdef TARGET_WORDS_BIGENDIAN
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val = io_mem_read(io_index, addr, 4) << 32;
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val |= io_mem_read(io_index, addr + 4, 4);
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val = io_mem_read(section->mr, addr, 4) << 32;
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val |= io_mem_read(section->mr, addr + 4, 4);
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#else
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val = io_mem_read(io_index, addr, 4);
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val |= io_mem_read(io_index, addr + 4, 4) << 32;
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val = io_mem_read(section->mr, addr, 4);
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val |= io_mem_read(section->mr, addr + 4, 4) << 32;
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#endif
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} else {
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/* RAM case */
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@ -4236,7 +4222,6 @@ uint32_t ldub_phys(target_phys_addr_t addr)
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static inline uint32_t lduw_phys_internal(target_phys_addr_t addr,
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enum device_endian endian)
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{
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int io_index;
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uint8_t *ptr;
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uint64_t val;
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MemoryRegionSection *section;
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@ -4245,10 +4230,8 @@ static inline uint32_t lduw_phys_internal(target_phys_addr_t addr,
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if (!is_ram_rom_romd(section)) {
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/* I/O case */
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io_index = memory_region_get_ram_addr(section->mr)
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& (IO_MEM_NB_ENTRIES - 1);
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addr = section_addr(section, addr);
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val = io_mem_read(io_index, addr, 2);
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val = io_mem_read(section->mr, addr, 2);
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap16(val);
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@ -4298,20 +4281,17 @@ uint32_t lduw_be_phys(target_phys_addr_t addr)
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bits are used to track modified PTEs */
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void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
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{
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int io_index;
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uint8_t *ptr;
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MemoryRegionSection *section;
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section = phys_page_find(addr >> TARGET_PAGE_BITS);
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if (!memory_region_is_ram(section->mr) || section->readonly) {
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if (memory_region_is_ram(section->mr)) {
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io_index = io_mem_rom.ram_addr;
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} else {
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io_index = memory_region_get_ram_addr(section->mr);
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}
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addr = section_addr(section, addr);
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io_mem_write(io_index, addr, val, 4);
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if (memory_region_is_ram(section->mr)) {
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section = &phys_sections[phys_section_rom];
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}
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io_mem_write(section->mr, addr, val, 4);
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} else {
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unsigned long addr1 = (memory_region_get_ram_addr(section->mr)
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& TARGET_PAGE_MASK)
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@ -4333,26 +4313,22 @@ void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
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void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
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{
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int io_index;
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uint8_t *ptr;
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MemoryRegionSection *section;
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section = phys_page_find(addr >> TARGET_PAGE_BITS);
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if (!memory_region_is_ram(section->mr) || section->readonly) {
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if (memory_region_is_ram(section->mr)) {
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io_index = io_mem_rom.ram_addr;
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} else {
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io_index = memory_region_get_ram_addr(section->mr)
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& (IO_MEM_NB_ENTRIES - 1);
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}
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addr = section_addr(section, addr);
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if (memory_region_is_ram(section->mr)) {
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section = &phys_sections[phys_section_rom];
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}
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#ifdef TARGET_WORDS_BIGENDIAN
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io_mem_write(io_index, addr, val >> 32, 4);
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io_mem_write(io_index, addr + 4, (uint32_t)val, 4);
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io_mem_write(section->mr, addr, val >> 32, 4);
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io_mem_write(section->mr, addr + 4, (uint32_t)val, 4);
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#else
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io_mem_write(io_index, addr, (uint32_t)val, 4);
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io_mem_write(io_index, addr + 4, val >> 32, 4);
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io_mem_write(section->mr, addr, (uint32_t)val, 4);
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io_mem_write(section->mr, addr + 4, val >> 32, 4);
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#endif
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} else {
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ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(section->mr)
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@ -4366,20 +4342,16 @@ void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
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static inline void stl_phys_internal(target_phys_addr_t addr, uint32_t val,
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enum device_endian endian)
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{
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int io_index;
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uint8_t *ptr;
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MemoryRegionSection *section;
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section = phys_page_find(addr >> TARGET_PAGE_BITS);
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if (!memory_region_is_ram(section->mr) || section->readonly) {
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if (memory_region_is_ram(section->mr)) {
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io_index = io_mem_rom.ram_addr;
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} else {
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io_index = memory_region_get_ram_addr(section->mr)
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& (IO_MEM_NB_ENTRIES - 1);
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}
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addr = section_addr(section, addr);
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if (memory_region_is_ram(section->mr)) {
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section = &phys_sections[phys_section_rom];
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}
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap32(val);
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@ -4389,7 +4361,7 @@ static inline void stl_phys_internal(target_phys_addr_t addr, uint32_t val,
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val = bswap32(val);
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}
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#endif
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io_mem_write(io_index, addr, val, 4);
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io_mem_write(section->mr, addr, val, 4);
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} else {
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unsigned long addr1;
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addr1 = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK)
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@ -4443,20 +4415,16 @@ void stb_phys(target_phys_addr_t addr, uint32_t val)
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static inline void stw_phys_internal(target_phys_addr_t addr, uint32_t val,
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enum device_endian endian)
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{
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int io_index;
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uint8_t *ptr;
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MemoryRegionSection *section;
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section = phys_page_find(addr >> TARGET_PAGE_BITS);
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if (!memory_region_is_ram(section->mr) || section->readonly) {
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if (memory_region_is_ram(section->mr)) {
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io_index = io_mem_rom.ram_addr;
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} else {
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io_index = memory_region_get_ram_addr(section->mr)
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& (IO_MEM_NB_ENTRIES - 1);
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}
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addr = section_addr(section, addr);
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if (memory_region_is_ram(section->mr)) {
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section = &phys_sections[phys_section_rom];
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}
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap16(val);
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@ -4466,7 +4434,7 @@ static inline void stw_phys_internal(target_phys_addr_t addr, uint32_t val,
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val = bswap16(val);
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}
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#endif
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io_mem_write(io_index, addr, val, 2);
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io_mem_write(section->mr, addr, val, 2);
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} else {
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unsigned long addr1;
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addr1 = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK)
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@ -4678,6 +4646,7 @@ tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
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{
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int mmu_idx, page_index, pd;
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void *p;
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MemoryRegion *mr;
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page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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mmu_idx = cpu_mmu_index(env1);
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@ -4686,8 +4655,9 @@ tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
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ldub_code(addr);
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}
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pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
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if (pd != io_mem_ram.ram_addr && pd != io_mem_rom.ram_addr
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&& !io_mem_region[pd]->rom_device) {
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mr = iotlb_to_region(pd);
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if (mr != &io_mem_ram && mr != &io_mem_rom
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&& mr != &io_mem_notdirty && !mr->rom_device) {
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#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SPARC)
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cpu_unassigned_access(env1, addr, 0, 1, 0, 4);
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#else
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8
memory.c
8
memory.c
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@ -1501,15 +1501,15 @@ void set_system_io_map(MemoryRegion *mr)
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memory_region_update_topology(NULL);
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}
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uint64_t io_mem_read(int io_index, target_phys_addr_t addr, unsigned size)
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uint64_t io_mem_read(MemoryRegion *mr, target_phys_addr_t addr, unsigned size)
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{
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return memory_region_dispatch_read(io_mem_region[io_index], addr, size);
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return memory_region_dispatch_read(mr, addr, size);
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}
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void io_mem_write(int io_index, target_phys_addr_t addr,
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void io_mem_write(MemoryRegion *mr, target_phys_addr_t addr,
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uint64_t val, unsigned size)
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{
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memory_region_dispatch_write(io_mem_region[io_index], addr, val, size);
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memory_region_dispatch_write(mr, addr, val, size);
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}
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typedef struct MemoryRegionList MemoryRegionList;
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@ -62,27 +62,27 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
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void *retaddr)
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{
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DATA_TYPE res;
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int index;
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index = physaddr & (IO_MEM_NB_ENTRIES - 1);
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MemoryRegion *mr = iotlb_to_region(physaddr);
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physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
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env->mem_io_pc = (unsigned long)retaddr;
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if (index != io_mem_ram.ram_addr && index != io_mem_rom.ram_addr
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&& index != io_mem_unassigned.ram_addr
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&& index != io_mem_notdirty.ram_addr
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if (mr != &io_mem_ram && mr != &io_mem_rom
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&& mr != &io_mem_unassigned
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&& mr != &io_mem_notdirty
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&& !can_do_io(env)) {
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cpu_io_recompile(env, retaddr);
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}
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env->mem_io_vaddr = addr;
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#if SHIFT <= 2
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res = io_mem_read(index, physaddr, 1 << SHIFT);
|
||||
res = io_mem_read(mr, physaddr, 1 << SHIFT);
|
||||
#else
|
||||
#ifdef TARGET_WORDS_BIGENDIAN
|
||||
res = io_mem_read(index, physaddr, 4) << 32;
|
||||
res |= io_mem_read(index, physaddr + 4, 4);
|
||||
res = io_mem_read(mr, physaddr, 4) << 32;
|
||||
res |= io_mem_read(mr, physaddr + 4, 4);
|
||||
#else
|
||||
res = io_mem_read(index, physaddr, 4);
|
||||
res |= io_mem_read(index, physaddr + 4, 4) << 32;
|
||||
res = io_mem_read(mr, physaddr, 4);
|
||||
res |= io_mem_read(mr, physaddr + 4, 4) << 32;
|
||||
#endif
|
||||
#endif /* SHIFT > 2 */
|
||||
return res;
|
||||
|
|
@ -110,7 +110,7 @@ DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
|
|||
if ((addr & (DATA_SIZE - 1)) != 0)
|
||||
goto do_unaligned_access;
|
||||
retaddr = GETPC();
|
||||
ioaddr = section_to_ioaddr(env->iotlb[mmu_idx][index]);
|
||||
ioaddr = env->iotlb[mmu_idx][index];
|
||||
res = glue(io_read, SUFFIX)(ioaddr, addr, retaddr);
|
||||
} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
|
||||
/* slow unaligned access (it spans two pages or IO) */
|
||||
|
|
@ -164,7 +164,7 @@ static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
|
|||
/* IO access */
|
||||
if ((addr & (DATA_SIZE - 1)) != 0)
|
||||
goto do_unaligned_access;
|
||||
ioaddr = section_to_ioaddr(env->iotlb[mmu_idx][index]);
|
||||
ioaddr = env->iotlb[mmu_idx][index];
|
||||
res = glue(io_read, SUFFIX)(ioaddr, addr, retaddr);
|
||||
} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
|
||||
do_unaligned_access:
|
||||
|
|
@ -207,12 +207,12 @@ static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
|
|||
target_ulong addr,
|
||||
void *retaddr)
|
||||
{
|
||||
int index;
|
||||
index = physaddr & (IO_MEM_NB_ENTRIES - 1);
|
||||
MemoryRegion *mr = iotlb_to_region(physaddr);
|
||||
|
||||
physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
|
||||
if (index != io_mem_ram.ram_addr && index != io_mem_rom.ram_addr
|
||||
&& index != io_mem_unassigned.ram_addr
|
||||
&& index != io_mem_notdirty.ram_addr
|
||||
if (mr != &io_mem_ram && mr != &io_mem_rom
|
||||
&& mr != &io_mem_unassigned
|
||||
&& mr != &io_mem_notdirty
|
||||
&& !can_do_io(env)) {
|
||||
cpu_io_recompile(env, retaddr);
|
||||
}
|
||||
|
|
@ -220,14 +220,14 @@ static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
|
|||
env->mem_io_vaddr = addr;
|
||||
env->mem_io_pc = (unsigned long)retaddr;
|
||||
#if SHIFT <= 2
|
||||
io_mem_write(index, physaddr, val, 1 << SHIFT);
|
||||
io_mem_write(mr, physaddr, val, 1 << SHIFT);
|
||||
#else
|
||||
#ifdef TARGET_WORDS_BIGENDIAN
|
||||
io_mem_write(index, physaddr, (val >> 32), 4);
|
||||
io_mem_write(index, physaddr + 4, (uint32_t)val, 4);
|
||||
io_mem_write(mr, physaddr, (val >> 32), 4);
|
||||
io_mem_write(mr, physaddr + 4, (uint32_t)val, 4);
|
||||
#else
|
||||
io_mem_write(index, physaddr, (uint32_t)val, 4);
|
||||
io_mem_write(index, physaddr + 4, val >> 32, 4);
|
||||
io_mem_write(mr, physaddr, (uint32_t)val, 4);
|
||||
io_mem_write(mr, physaddr + 4, val >> 32, 4);
|
||||
#endif
|
||||
#endif /* SHIFT > 2 */
|
||||
}
|
||||
|
|
@ -251,7 +251,7 @@ void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
|
|||
if ((addr & (DATA_SIZE - 1)) != 0)
|
||||
goto do_unaligned_access;
|
||||
retaddr = GETPC();
|
||||
ioaddr = section_to_ioaddr(env->iotlb[mmu_idx][index]);
|
||||
ioaddr = env->iotlb[mmu_idx][index];
|
||||
glue(io_write, SUFFIX)(ioaddr, val, addr, retaddr);
|
||||
} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
|
||||
do_unaligned_access:
|
||||
|
|
@ -303,7 +303,7 @@ static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
|
|||
/* IO access */
|
||||
if ((addr & (DATA_SIZE - 1)) != 0)
|
||||
goto do_unaligned_access;
|
||||
ioaddr = section_to_ioaddr(env->iotlb[mmu_idx][index]);
|
||||
ioaddr = env->iotlb[mmu_idx][index];
|
||||
glue(io_write, SUFFIX)(ioaddr, val, addr, retaddr);
|
||||
} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
|
||||
do_unaligned_access:
|
||||
|
|
|
|||
Loading…
Reference in a new issue