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https://gitlab.com/qemu-project/qemu
synced 2024-10-15 07:22:46 +00:00
tcg-i386: Use TCGMemOp within qemu_ldst routines
Step one in the transition, with constants passed down from tcg_out_op. Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
d257e0d7ae
commit
37c5d0d5d1
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@ -1077,7 +1077,7 @@ static void add_qemu_ldst_label(TCGContext *s,
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First argument register is clobbered. */
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static inline void tcg_out_tlb_load(TCGContext *s, int addrlo_idx,
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int mem_index, int s_bits,
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int mem_index, TCGMemOp s_bits,
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const TCGArg *args,
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uint8_t **label_ptr, int which)
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{
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@ -1164,28 +1164,26 @@ static inline void setup_guest_base_seg(void)
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static inline void setup_guest_base_seg(void) { }
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#endif /* SOFTMMU */
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static void tcg_out_qemu_ld_direct(TCGContext *s, int datalo, int datahi,
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int base, intptr_t ofs, int seg, int sizeop)
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static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
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TCGReg base, intptr_t ofs, int seg,
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TCGMemOp memop)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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const int bswap = 1;
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#else
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const int bswap = 0;
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#endif
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switch (sizeop) {
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case 0:
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const TCGMemOp bswap = memop & MO_BSWAP;
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switch (memop & MO_SSIZE) {
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case MO_UB:
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tcg_out_modrm_offset(s, OPC_MOVZBL + seg, datalo, base, ofs);
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break;
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case 0 | 4:
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case MO_SB:
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tcg_out_modrm_offset(s, OPC_MOVSBL + P_REXW + seg, datalo, base, ofs);
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break;
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case 1:
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case MO_UW:
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tcg_out_modrm_offset(s, OPC_MOVZWL + seg, datalo, base, ofs);
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if (bswap) {
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tcg_out_rolw_8(s, datalo);
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}
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break;
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case 1 | 4:
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case MO_SW:
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if (bswap) {
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tcg_out_modrm_offset(s, OPC_MOVZWL + seg, datalo, base, ofs);
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tcg_out_rolw_8(s, datalo);
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@ -1195,14 +1193,14 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, int datalo, int datahi,
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datalo, base, ofs);
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}
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break;
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case 2:
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case MO_UL:
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tcg_out_modrm_offset(s, OPC_MOVL_GvEv + seg, datalo, base, ofs);
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if (bswap) {
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tcg_out_bswap32(s, datalo);
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}
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break;
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#if TCG_TARGET_REG_BITS == 64
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case 2 | 4:
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case MO_SL:
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if (bswap) {
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tcg_out_modrm_offset(s, OPC_MOVL_GvEv + seg, datalo, base, ofs);
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tcg_out_bswap32(s, datalo);
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@ -1212,7 +1210,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, int datalo, int datahi,
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}
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break;
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#endif
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case 3:
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case MO_Q:
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if (TCG_TARGET_REG_BITS == 64) {
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tcg_out_modrm_offset(s, OPC_MOVL_GvEv + P_REXW + seg,
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datalo, base, ofs);
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@ -1250,26 +1248,26 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, int datalo, int datahi,
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/* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and
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EAX. It will be useful once fixed registers globals are less
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common. */
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static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
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int opc)
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static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGMemOp opc)
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{
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int data_reg, data_reg2 = 0;
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int addrlo_idx;
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#if defined(CONFIG_SOFTMMU)
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int mem_index, s_bits;
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int mem_index;
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TCGMemOp s_bits;
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uint8_t *label_ptr[2];
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#endif
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data_reg = args[0];
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addrlo_idx = 1;
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if (TCG_TARGET_REG_BITS == 32 && opc == 3) {
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if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
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data_reg2 = args[1];
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addrlo_idx = 2;
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}
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#if defined(CONFIG_SOFTMMU)
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mem_index = args[addrlo_idx + 1 + (TARGET_LONG_BITS > TCG_TARGET_REG_BITS)];
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s_bits = opc & 3;
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s_bits = opc & MO_SIZE;
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tcg_out_tlb_load(s, addrlo_idx, mem_index, s_bits, args,
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label_ptr, offsetof(CPUTLBEntry, addr_read));
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@ -1314,27 +1312,24 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
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#endif
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}
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static void tcg_out_qemu_st_direct(TCGContext *s, int datalo, int datahi,
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int base, intptr_t ofs, int seg,
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int sizeop)
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static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
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TCGReg base, intptr_t ofs, int seg,
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TCGMemOp memop)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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const int bswap = 1;
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#else
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const int bswap = 0;
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#endif
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const TCGMemOp bswap = memop & MO_BSWAP;
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/* ??? Ideally we wouldn't need a scratch register. For user-only,
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we could perform the bswap twice to restore the original value
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instead of moving to the scratch. But as it is, the L constraint
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means that TCG_REG_L0 is definitely free here. */
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const int scratch = TCG_REG_L0;
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const TCGReg scratch = TCG_REG_L0;
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switch (sizeop) {
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case 0:
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switch (memop & MO_SIZE) {
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case MO_8:
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tcg_out_modrm_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg,
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datalo, base, ofs);
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break;
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case 1:
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case MO_16:
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if (bswap) {
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tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);
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tcg_out_rolw_8(s, scratch);
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@ -1343,7 +1338,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int datalo, int datahi,
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tcg_out_modrm_offset(s, OPC_MOVL_EvGv + P_DATA16 + seg,
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datalo, base, ofs);
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break;
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case 2:
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case MO_32:
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if (bswap) {
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tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);
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tcg_out_bswap32(s, scratch);
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@ -1351,7 +1346,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int datalo, int datahi,
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}
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tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, datalo, base, ofs);
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break;
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case 3:
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case MO_64:
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if (TCG_TARGET_REG_BITS == 64) {
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if (bswap) {
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tcg_out_mov(s, TCG_TYPE_I64, scratch, datalo);
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@ -1377,13 +1372,13 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int datalo, int datahi,
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}
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}
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static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
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int opc)
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static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGMemOp opc)
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{
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int data_reg, data_reg2 = 0;
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int addrlo_idx;
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#if defined(CONFIG_SOFTMMU)
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int mem_index, s_bits;
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int mem_index;
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TCGMemOp s_bits;
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uint8_t *label_ptr[2];
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#endif
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@ -1396,7 +1391,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
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#if defined(CONFIG_SOFTMMU)
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mem_index = args[addrlo_idx + 1 + (TARGET_LONG_BITS > TCG_TARGET_REG_BITS)];
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s_bits = opc;
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s_bits = opc & MO_SIZE;
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tcg_out_tlb_load(s, addrlo_idx, mem_index, s_bits, args,
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label_ptr, offsetof(CPUTLBEntry, addr_write));
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@ -1478,8 +1473,8 @@ static void add_qemu_ldst_label(TCGContext *s,
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*/
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static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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{
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int opc = l->opc;
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int s_bits = opc & 3;
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TCGMemOp opc = l->opc;
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TCGMemOp s_bits = opc & MO_SIZE;
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TCGReg data_reg;
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uint8_t **label_ptr = &l->label_ptr[0];
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@ -1519,25 +1514,25 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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tcg_out_calli(s, (uintptr_t)qemu_ld_helpers[s_bits]);
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data_reg = l->datalo_reg;
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switch(opc) {
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case 0 | 4:
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switch (opc & MO_SSIZE) {
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case MO_SB:
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tcg_out_ext8s(s, data_reg, TCG_REG_EAX, P_REXW);
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break;
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case 1 | 4:
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case MO_SW:
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tcg_out_ext16s(s, data_reg, TCG_REG_EAX, P_REXW);
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break;
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#if TCG_TARGET_REG_BITS == 64
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case 2 | 4:
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case MO_SL:
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tcg_out_ext32s(s, data_reg, TCG_REG_EAX);
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break;
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#endif
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case 0:
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case 1:
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case MO_UB:
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case MO_UW:
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/* Note that the helpers have zero-extended to tcg_target_long. */
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case 2:
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case MO_UL:
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tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX);
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break;
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case 3:
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case MO_Q:
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if (TCG_TARGET_REG_BITS == 64) {
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tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_RAX);
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} else if (data_reg == TCG_REG_EDX) {
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@ -1562,8 +1557,8 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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*/
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static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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{
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int opc = l->opc;
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int s_bits = opc & 3;
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TCGMemOp opc = l->opc;
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TCGMemOp s_bits = opc & MO_SIZE;
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uint8_t **label_ptr = &l->label_ptr[0];
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TCGReg retaddr;
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@ -1590,7 +1585,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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tcg_out_st(s, TCG_TYPE_I32, l->datalo_reg, TCG_REG_ESP, ofs);
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ofs += 4;
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if (opc == 3) {
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if (s_bits == MO_64) {
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tcg_out_st(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_ESP, ofs);
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ofs += 4;
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}
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@ -1604,7 +1599,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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} else {
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tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
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/* The second argument is already loaded with addrlo. */
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tcg_out_mov(s, (opc == 3 ? TCG_TYPE_I64 : TCG_TYPE_I32),
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tcg_out_mov(s, (s_bits == MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
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tcg_target_call_iarg_regs[2], l->datalo_reg);
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tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
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l->mem_index);
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@ -1851,38 +1846,38 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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break;
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case INDEX_op_qemu_ld8u:
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tcg_out_qemu_ld(s, args, 0);
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tcg_out_qemu_ld(s, args, MO_UB);
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break;
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case INDEX_op_qemu_ld8s:
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tcg_out_qemu_ld(s, args, 0 | 4);
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tcg_out_qemu_ld(s, args, MO_SB);
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break;
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case INDEX_op_qemu_ld16u:
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tcg_out_qemu_ld(s, args, 1);
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tcg_out_qemu_ld(s, args, MO_TEUW);
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break;
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case INDEX_op_qemu_ld16s:
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tcg_out_qemu_ld(s, args, 1 | 4);
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tcg_out_qemu_ld(s, args, MO_TESW);
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break;
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#if TCG_TARGET_REG_BITS == 64
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case INDEX_op_qemu_ld32u:
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#endif
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case INDEX_op_qemu_ld32:
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tcg_out_qemu_ld(s, args, 2);
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tcg_out_qemu_ld(s, args, MO_TEUL);
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break;
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case INDEX_op_qemu_ld64:
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tcg_out_qemu_ld(s, args, 3);
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tcg_out_qemu_ld(s, args, MO_TEQ);
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break;
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case INDEX_op_qemu_st8:
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tcg_out_qemu_st(s, args, 0);
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tcg_out_qemu_st(s, args, MO_UB);
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break;
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case INDEX_op_qemu_st16:
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tcg_out_qemu_st(s, args, 1);
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tcg_out_qemu_st(s, args, MO_TEUW);
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break;
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case INDEX_op_qemu_st32:
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tcg_out_qemu_st(s, args, 2);
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tcg_out_qemu_st(s, args, MO_TEUL);
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break;
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case INDEX_op_qemu_st64:
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tcg_out_qemu_st(s, args, 3);
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tcg_out_qemu_st(s, args, MO_TEQ);
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break;
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OP_32_64(mulu2):
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@ -1943,7 +1938,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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}
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break;
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case INDEX_op_qemu_ld32s:
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tcg_out_qemu_ld(s, args, 2 | 4);
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tcg_out_qemu_ld(s, args, MO_TESL);
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break;
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case INDEX_op_brcond_i64:
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