mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-09-06 09:55:55 +00:00
MIPS FPU dynamic activation, part 1, by Herve Poussineau.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2463 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
parent
54d43f70e3
commit
36d2395873
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@ -581,13 +581,12 @@ static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
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}
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pd = env->tlb_table[is_user][index].addr_code & ~TARGET_PAGE_MASK;
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if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
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cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
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cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
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}
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return addr + env->tlb_table[is_user][index].addend - (unsigned long)phys_ram_base;
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}
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#endif
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#ifdef USE_KQEMU
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#define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))
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50
gdbstub.c
50
gdbstub.c
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@ -568,20 +568,21 @@ static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
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*(uint32_t *)ptr = tswapl(env->PC);
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ptr += 4;
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#ifdef MIPS_USES_FPU
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for (i = 0; i < 32; i++)
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if (env->CP0_Config1 & (1 << CP0C1_FP))
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{
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*(uint32_t *)ptr = tswapl(FPR_W (env, i));
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for (i = 0; i < 32; i++)
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{
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*(uint32_t *)ptr = tswapl(FPR_W (env, i));
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ptr += 4;
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}
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*(uint32_t *)ptr = tswapl(env->fcr31);
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ptr += 4;
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*(uint32_t *)ptr = tswapl(env->fcr0);
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ptr += 4;
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}
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*(uint32_t *)ptr = tswapl(env->fcr31);
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ptr += 4;
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*(uint32_t *)ptr = tswapl(env->fcr0);
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ptr += 4;
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#endif
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/* 32 FP registers, fsr, fir, fp. Not yet implemented. */
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/* what's 'fp' mean here? */
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@ -629,27 +630,28 @@ static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
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env->PC = tswapl(*(uint32_t *)ptr);
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ptr += 4;
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#ifdef MIPS_USES_FPU
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for (i = 0; i < 32; i++)
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if (env->CP0_Config1 & (1 << CP0C1_FP))
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{
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FPR_W (env, i) = tswapl(*(uint32_t *)ptr);
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for (i = 0; i < 32; i++)
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{
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FPR_W (env, i) = tswapl(*(uint32_t *)ptr);
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ptr += 4;
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}
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env->fcr31 = tswapl(*(uint32_t *)ptr) & 0x0183FFFF;
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ptr += 4;
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}
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env->fcr31 = tswapl(*(uint32_t *)ptr) & 0x0183FFFF;
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ptr += 4;
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env->fcr0 = tswapl(*(uint32_t *)ptr);
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ptr += 4;
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env->fcr0 = tswapl(*(uint32_t *)ptr);
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ptr += 4;
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/* set rounding mode */
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RESTORE_ROUNDING_MODE;
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/* set rounding mode */
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RESTORE_ROUNDING_MODE;
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#ifndef CONFIG_SOFTFLOAT
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/* no floating point exception for native float */
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SET_FP_ENABLE(env->fcr31, 0);
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#endif
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/* no floating point exception for native float */
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SET_FP_ENABLE(env->fcr31, 0);
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#endif
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}
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}
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#elif defined (TARGET_SH4)
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static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
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@ -1838,9 +1838,9 @@ int main(int argc, char **argv)
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env->gpr[i] = regs->regs[i];
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}
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env->PC = regs->cp0_epc;
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#ifdef MIPS_USES_FPU
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env->CP0_Status |= (1 << CP0St_CU1);
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#endif
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if (env->CP0_Config1 & (1 << CP0C1_FP)) {
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env->CP0_Status |= (1 << CP0St_CU1);
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}
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}
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#elif defined(TARGET_SH4)
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{
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@ -63,7 +63,6 @@ struct CPUMIPSState {
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#endif
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target_ulong HI, LO;
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uint32_t DCR; /* ? */
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#if defined(MIPS_USES_FPU)
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/* Floating point registers */
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fpr_t fpr[16];
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#define FPR(cpu, n) ((fpr_t*)&(cpu)->fpr[(n) / 2])
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@ -97,8 +96,7 @@ struct CPUMIPSState {
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#define FP_DIV0 8
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#define FP_INVALID 16
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#define FP_UNIMPLEMENTED 32
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#endif
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#if defined(MIPS_USES_R4K_TLB)
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tlb_t tlb[MIPS_TLB_MAX];
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uint32_t tlb_in_use;
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@ -115,12 +115,10 @@ void do_tlbwi (void);
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void do_tlbwr (void);
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void do_tlbp (void);
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void do_tlbr (void);
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#ifdef MIPS_USES_FPU
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void dump_fpu(CPUState *env);
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void fpu_dump_state(CPUState *env, FILE *f,
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int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
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int flags);
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#endif
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void dump_sc (void);
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void do_lwl_raw (uint32_t);
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void do_lwr_raw (uint32_t);
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@ -45,19 +45,14 @@
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2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
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no coprocessor2 attached, no MDMX support attached,
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no performance counters, watch registers present,
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no code compression, EJTAG present, FPU enable bit depending on
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MIPS_USES_FPU */
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#define MIPS_CONFIG1_1 \
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no code compression, EJTAG present, no FPU */
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#define MIPS_CONFIG1 \
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((1 << CP0C1_M) | ((MIPS_TLB_NB - 1) << CP0C1_MMU) | \
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(0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) | \
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(0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) | \
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(0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
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(1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP))
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#ifdef MIPS_USES_FPU
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#define MIPS_CONFIG1 (MIPS_CONFIG1_1 | (1 << CP0C1_FP))
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#else
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#define MIPS_CONFIG1 (MIPS_CONFIG1_1 | (0 << CP0C1_FP))
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#endif
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(1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
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(0 << CP0C1_FP))
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/* Have config3, no tertiary/secondary caches implemented */
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#define MIPS_CONFIG2 \
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((1 << CP0C2_M))
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@ -144,8 +144,6 @@ CALL_FROM_TB2(func, arg0, arg1);
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#include "op_template.c"
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#undef TN
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#ifdef MIPS_USES_FPU
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#define SFREG 0
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#define DFREG 0
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#include "fop_template.c"
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#include "fop_template.c"
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#undef FTN
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#endif
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void op_dup_T0 (void)
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{
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T2 = T0;
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@ -924,7 +920,6 @@ void op_movz (void)
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RETURN();
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}
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#ifdef MIPS_USES_FPU
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void op_movf (void)
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{
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if (!(env->fcr31 & PARAM1))
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@ -938,7 +933,6 @@ void op_movt (void)
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env->gpr[PARAM2] = env->gpr[PARAM3];
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RETURN();
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}
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#endif
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/* Tests */
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#define OP_COND(name, cond) \
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RETURN();
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}
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#ifdef MIPS_USES_FPU
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#if 0
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# define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
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#else
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@ -2001,7 +1993,6 @@ void op_bc1t (void)
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DEBUG_FPU_STATE();
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RETURN();
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}
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#endif /* MIPS_USES_FPU */
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#if defined(MIPS_USES_R4K_TLB)
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void op_tlbwi (void)
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@ -331,7 +331,6 @@ void do_mtc0_status_irqraise_debug(void)
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fprintf(logfile, "Raise pending IRQs\n");
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}
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#ifdef MIPS_USES_FPU
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#include "softfloat.h"
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void fpu_handle_exception(void)
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SET_FP_CAUSE(env->fcr31, 0);
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#endif
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}
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#endif /* MIPS_USES_FPU */
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/* TLB management */
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#if defined(MIPS_USES_R4K_TLB)
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@ -192,7 +192,6 @@ void glue(op_scd, MEMSUFFIX) (void)
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}
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#endif /* MIPS_HAS_MIPS64 */
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#ifdef MIPS_USES_FPU
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void glue(op_lwc1, MEMSUFFIX) (void)
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{
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WT0 = glue(ldl, MEMSUFFIX)(T0);
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@ -213,4 +212,3 @@ void glue(op_sdc1, MEMSUFFIX) (void)
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glue(stq, MEMSUFFIX)(T0, DT0);
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RETURN();
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}
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#endif
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@ -391,8 +391,6 @@ GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
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GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
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GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
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#ifdef MIPS_USES_FPU
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static const char *fregnames[] =
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{ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
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"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
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@ -476,8 +474,6 @@ static inline void gen_cmp_ ## fmt(int n) \
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FOP_CONDS(d)
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FOP_CONDS(s)
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#endif /* MIPS_USES_FPU */
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typedef struct DisasContext {
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struct TranslationBlock *tb;
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target_ulong pc, saved_pc;
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@ -640,12 +636,10 @@ OP_LD_TABLE(bu);
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OP_ST_TABLE(b);
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OP_LD_TABLE(l);
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OP_ST_TABLE(c);
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#ifdef MIPS_USES_FPU
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OP_LD_TABLE(wc1);
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OP_ST_TABLE(wc1);
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OP_LD_TABLE(dc1);
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OP_ST_TABLE(dc1);
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#endif
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/* Load and store */
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static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
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@ -794,8 +788,6 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
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MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
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}
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#ifdef MIPS_USES_FPU
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/* Load and store */
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static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
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int base, int16_t offset)
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@ -843,8 +835,6 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
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MIPS_DEBUG("%s %s, %d(%s)", opn, fregnames[ft], offset, regnames[base]);
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}
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#endif /* MIPS_USES_FPU */
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/* Arithmetic with immediate operand */
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static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt,
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int rs, int16_t imm)
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@ -4111,8 +4101,6 @@ static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd)
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MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd);
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}
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#ifdef MIPS_USES_FPU
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/* CP1 Branches (before delay slot) */
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static void gen_compute_branch1 (DisasContext *ctx, uint32_t op,
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int32_t offset)
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@ -4531,8 +4519,6 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
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gen_op_movt(ccbit, rd, rs);
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}
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#endif /* MIPS_USES_FPU */
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/* ISA extensions (ASEs) */
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/* MIPS16 extension to MIPS32 */
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/* SmartMIPS extension to MIPS32 */
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@ -4555,7 +4541,7 @@ static void gen_blikely(DisasContext *ctx)
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gen_set_label(l1);
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}
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static void decode_opc (DisasContext *ctx)
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static void decode_opc (CPUState *env, DisasContext *ctx)
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{
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int32_t offset;
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int rs, rt, rd, sa;
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@ -4631,13 +4617,15 @@ static void decode_opc (DisasContext *ctx)
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/* Treat as a noop. */
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break;
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#ifdef MIPS_USES_FPU
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case OPC_MOVCI:
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gen_op_cp1_enabled();
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gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
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(ctx->opcode >> 16) & 1);
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if (env->CP0_Config1 & (1 << CP0C1_FP)) {
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gen_op_cp1_enabled();
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gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
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(ctx->opcode >> 16) & 1);
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} else {
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generate_exception(ctx, EXCP_RI);
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}
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break;
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#endif
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#ifdef MIPS_HAS_MIPS64
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/* MIPS64 specific opcodes */
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@ -4868,47 +4856,47 @@ static void decode_opc (DisasContext *ctx)
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case OPC_LDC1:
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case OPC_SWC1:
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case OPC_SDC1:
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#if defined(MIPS_USES_FPU)
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save_cpu_state(ctx, 1);
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gen_op_cp1_enabled();
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gen_flt_ldst(ctx, op, rt, rs, imm);
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#else
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generate_exception_err(ctx, EXCP_CpU, 1);
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#endif
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if (env->CP0_Config1 & (1 << CP0C1_FP)) {
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save_cpu_state(ctx, 1);
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gen_op_cp1_enabled();
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gen_flt_ldst(ctx, op, rt, rs, imm);
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} else {
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generate_exception_err(ctx, EXCP_CpU, 1);
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}
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break;
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case OPC_CP1:
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#if defined(MIPS_USES_FPU)
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save_cpu_state(ctx, 1);
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gen_op_cp1_enabled();
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op1 = MASK_CP1(ctx->opcode);
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switch (op1) {
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case OPC_MFC1:
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case OPC_CFC1:
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case OPC_MTC1:
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case OPC_CTC1:
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if (env->CP0_Config1 & (1 << CP0C1_FP)) {
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save_cpu_state(ctx, 1);
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gen_op_cp1_enabled();
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op1 = MASK_CP1(ctx->opcode);
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switch (op1) {
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case OPC_MFC1:
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case OPC_CFC1:
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case OPC_MTC1:
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case OPC_CTC1:
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#ifdef MIPS_HAS_MIPS64
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case OPC_DMFC1:
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case OPC_DMTC1:
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case OPC_DMFC1:
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case OPC_DMTC1:
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#endif
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gen_cp1(ctx, op1, rt, rd);
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break;
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case OPC_BC1:
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gen_compute_branch1(ctx, MASK_CP1_BCOND(ctx->opcode), imm << 2);
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return;
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case OPC_S_FMT:
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case OPC_D_FMT:
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case OPC_W_FMT:
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case OPC_L_FMT:
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gen_farith(ctx, MASK_CP1_FUNC(ctx->opcode), rt, rd, sa);
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break;
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default:
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generate_exception_err(ctx, EXCP_RI, 1);
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break;
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gen_cp1(ctx, op1, rt, rd);
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break;
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case OPC_BC1:
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gen_compute_branch1(ctx, MASK_CP1_BCOND(ctx->opcode), imm << 2);
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return;
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case OPC_S_FMT:
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case OPC_D_FMT:
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case OPC_W_FMT:
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case OPC_L_FMT:
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gen_farith(ctx, MASK_CP1_FUNC(ctx->opcode), rt, rd, sa);
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break;
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default:
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generate_exception_err(ctx, EXCP_RI, 1);
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break;
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}
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} else {
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generate_exception_err(ctx, EXCP_CpU, 1);
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}
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#else
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generate_exception_err(ctx, EXCP_CpU, 1);
|
||||
#endif
|
||||
break;
|
||||
|
||||
/* COP2. */
|
||||
|
@ -4921,18 +4909,20 @@ static void decode_opc (DisasContext *ctx)
|
|||
generate_exception_err(ctx, EXCP_CpU, 2);
|
||||
break;
|
||||
|
||||
#ifdef MIPS_USES_FPU
|
||||
case OPC_CP3:
|
||||
gen_op_cp1_enabled();
|
||||
op1 = MASK_CP3(ctx->opcode);
|
||||
switch (op1) {
|
||||
/* Not implemented */
|
||||
default:
|
||||
generate_exception_err(ctx, EXCP_RI, 1);
|
||||
break;
|
||||
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
|
||||
gen_op_cp1_enabled();
|
||||
op1 = MASK_CP3(ctx->opcode);
|
||||
switch (op1) {
|
||||
/* Not implemented */
|
||||
default:
|
||||
generate_exception_err(ctx, EXCP_RI, 1);
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
generate_exception(ctx, EXCP_RI);
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef MIPS_HAS_MIPS64
|
||||
/* MIPS64 opcodes */
|
||||
|
@ -5079,7 +5069,7 @@ int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
|
|||
gen_opc_instr_start[lj] = 1;
|
||||
}
|
||||
ctx.opcode = ldl_code(ctx.pc);
|
||||
decode_opc(&ctx);
|
||||
decode_opc(env, &ctx);
|
||||
ctx.pc += 4;
|
||||
|
||||
if (env->singlestep_enabled)
|
||||
|
@ -5148,8 +5138,6 @@ int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
|
|||
return gen_intermediate_code_internal(env, tb, 1);
|
||||
}
|
||||
|
||||
#ifdef MIPS_USES_FPU
|
||||
|
||||
void fpu_dump_state(CPUState *env, FILE *f,
|
||||
int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
|
||||
int flags)
|
||||
|
@ -5184,8 +5172,6 @@ void dump_fpu (CPUState *env)
|
|||
}
|
||||
}
|
||||
|
||||
#endif /* MIPS_USES_FPU */
|
||||
|
||||
#if defined(MIPS_HAS_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
|
||||
/* Debug help: The architecture requires 32bit code to maintain proper
|
||||
sign-extened values on 64bit machines. */
|
||||
|
@ -5248,10 +5234,8 @@ void cpu_dump_state (CPUState *env, FILE *f,
|
|||
c0_status, env->CP0_Cause, env->CP0_EPC);
|
||||
cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx "\n",
|
||||
env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
|
||||
#ifdef MIPS_USES_FPU
|
||||
if (c0_status & (1 << CP0St_CU1))
|
||||
fpu_dump_state(env, f, cpu_fprintf, flags);
|
||||
#endif
|
||||
#if defined(MIPS_HAS_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
|
||||
cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags);
|
||||
#endif
|
||||
|
@ -5295,6 +5279,10 @@ void cpu_reset (CPUMIPSState *env)
|
|||
env->CP0_EBase = 0x80000000;
|
||||
env->CP0_Config0 = MIPS_CONFIG0;
|
||||
env->CP0_Config1 = MIPS_CONFIG1;
|
||||
#ifdef MIPS_USES_FPU
|
||||
/* basic FPU register support */
|
||||
env->CP0_Config1 |= (1 << CP0C1_FP);
|
||||
#endif
|
||||
env->CP0_Config2 = MIPS_CONFIG2;
|
||||
env->CP0_Config3 = MIPS_CONFIG3;
|
||||
env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
|
||||
|
@ -5309,9 +5297,7 @@ void cpu_reset (CPUMIPSState *env)
|
|||
env->hflags |= MIPS_HFLAG_UM;
|
||||
env->user_mode_only = 1;
|
||||
#endif
|
||||
#ifdef MIPS_USES_FPU
|
||||
env->fcr0 = MIPS_FCR0;
|
||||
#endif
|
||||
env->fcr0 = MIPS_FCR0;
|
||||
/* XXX some guesswork here, values are CPU specific */
|
||||
env->SYNCI_Step = 16;
|
||||
env->CCRes = 2;
|
||||
|
|
Loading…
Reference in a new issue