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target/riscv: rvv-1.0: add vsetivli instruction

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Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-73-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2021-12-10 15:56:58 +08:00 committed by Alistair Francis
parent 6b5c8eb3e7
commit 34a2c2d81a
2 changed files with 29 additions and 0 deletions
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2
target/riscv/insn32.decode
View file

@ -79,6 +79,7 @@
@r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd
@r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
@r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd
@r2_zimm10 .. zimm:10 ..... ... ..... ....... %rs1 %rd
@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
@ -672,6 +673,7 @@ vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm
vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11
vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
# *** RV32 Zba Standard Extension ***

27
target/riscv/insn_trans/trans_rvv.c.inc
View file

@ -160,6 +160,26 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
return true;
}
static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
{
TCGv dst;
if (!require_rvv(s) || !has_ext(s, RVV)) {
return false;
}
dst = dest_gpr(s, rd);
gen_helper_vsetvl(dst, cpu_env, s1, s2);
gen_set_gpr(s, rd, dst);
mark_vs_dirty(s);
tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn);
tcg_gen_lookup_and_goto_ptr();
s->base.is_jmp = DISAS_NORETURN;
return true;
}
static bool trans_vsetvl(DisasContext *s, arg_vsetvl *a)
{
TCGv s2 = get_gpr(s, a->rs2, EXT_ZERO);
@ -172,6 +192,13 @@ static bool trans_vsetvli(DisasContext *s, arg_vsetvli *a)
return do_vsetvl(s, a->rd, a->rs1, s2);
}
static bool trans_vsetivli(DisasContext *s, arg_vsetivli *a)
{
TCGv s1 = tcg_const_tl(a->rs1);
TCGv s2 = tcg_const_tl(a->zimm);
return do_vsetivli(s, a->rd, s1, s2);
}
/* vector register offset from env */
static uint32_t vreg_ofs(DisasContext *s, int reg)
{