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i386: Define the Virt SSBD MSR and handling of it (CVE-2018-3639)
"Some AMD processors only support a non-architectural means of enabling
speculative store bypass disable (SSBD). To allow a simplified view of
this to a guest, an architectural definition has been created through a new
CPUID bit, 0x80000008_EBX[25], and a new MSR, 0xc001011f. With this, a
hypervisor can virtualize the existence of this definition and provide an
architectural method for using SSBD to a guest.
Add the new CPUID feature, the new MSR and update the existing SSBD
support to use this MSR when present." (from x86/speculation: Add virtualized
speculative store bypass disable support in Linux).
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20180521215424.13520-4-berrange@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
(cherry picked from commit cfeea0c021
)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
This commit is contained in:
parent
8a302f42a5
commit
3129ddb943
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@ -351,6 +351,7 @@ typedef enum X86Seg {
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#define MSR_IA32_FEATURE_CONTROL 0x0000003a
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#define MSR_IA32_FEATURE_CONTROL 0x0000003a
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#define MSR_TSC_ADJUST 0x0000003b
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#define MSR_TSC_ADJUST 0x0000003b
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#define MSR_IA32_SPEC_CTRL 0x48
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#define MSR_IA32_SPEC_CTRL 0x48
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#define MSR_VIRT_SSBD 0xc001011f
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#define MSR_IA32_TSCDEADLINE 0x6e0
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#define MSR_IA32_TSCDEADLINE 0x6e0
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#define FEATURE_CONTROL_LOCKED (1<<0)
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#define FEATURE_CONTROL_LOCKED (1<<0)
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@ -1150,6 +1151,7 @@ typedef struct CPUX86State {
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uint32_t pkru;
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uint32_t pkru;
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uint64_t spec_ctrl;
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uint64_t spec_ctrl;
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uint64_t virt_ssbd;
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/* End of state preserved by INIT (dummy marker). */
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/* End of state preserved by INIT (dummy marker). */
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struct {} end_init_save;
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struct {} end_init_save;
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@ -92,6 +92,7 @@ static bool has_msr_hv_stimer;
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static bool has_msr_hv_frequencies;
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static bool has_msr_hv_frequencies;
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static bool has_msr_xss;
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static bool has_msr_xss;
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static bool has_msr_spec_ctrl;
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static bool has_msr_spec_ctrl;
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static bool has_msr_virt_ssbd;
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static bool has_msr_smi_count;
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static bool has_msr_smi_count;
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static uint32_t has_architectural_pmu_version;
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static uint32_t has_architectural_pmu_version;
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@ -1218,6 +1219,9 @@ static int kvm_get_supported_msrs(KVMState *s)
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case MSR_IA32_SPEC_CTRL:
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case MSR_IA32_SPEC_CTRL:
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has_msr_spec_ctrl = true;
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has_msr_spec_ctrl = true;
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break;
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break;
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case MSR_VIRT_SSBD:
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has_msr_virt_ssbd = true;
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break;
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}
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}
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}
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}
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}
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}
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@ -1706,6 +1710,10 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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if (has_msr_spec_ctrl) {
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if (has_msr_spec_ctrl) {
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kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
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kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
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}
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}
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if (has_msr_virt_ssbd) {
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kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
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}
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#ifdef TARGET_X86_64
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#ifdef TARGET_X86_64
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if (lm_capable_kernel) {
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if (lm_capable_kernel) {
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kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
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kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
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@ -2077,8 +2085,9 @@ static int kvm_get_msrs(X86CPU *cpu)
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if (has_msr_spec_ctrl) {
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if (has_msr_spec_ctrl) {
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kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
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kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
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}
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}
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if (has_msr_virt_ssbd) {
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kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
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}
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if (!env->tsc_valid) {
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if (!env->tsc_valid) {
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kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
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kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
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env->tsc_valid = !runstate_is_running();
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env->tsc_valid = !runstate_is_running();
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@ -2444,6 +2453,9 @@ static int kvm_get_msrs(X86CPU *cpu)
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case MSR_IA32_SPEC_CTRL:
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case MSR_IA32_SPEC_CTRL:
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env->spec_ctrl = msrs[i].data;
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env->spec_ctrl = msrs[i].data;
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break;
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break;
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case MSR_VIRT_SSBD:
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env->virt_ssbd = msrs[i].data;
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break;
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case MSR_IA32_RTIT_CTL:
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case MSR_IA32_RTIT_CTL:
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env->msr_rtit_ctrl = msrs[i].data;
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env->msr_rtit_ctrl = msrs[i].data;
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break;
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break;
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@ -893,6 +893,25 @@ static const VMStateDescription vmstate_msr_intel_pt = {
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}
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}
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};
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};
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static bool virt_ssbd_needed(void *opaque)
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{
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X86CPU *cpu = opaque;
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CPUX86State *env = &cpu->env;
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return env->virt_ssbd != 0;
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}
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static const VMStateDescription vmstate_msr_virt_ssbd = {
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.name = "cpu/virt_ssbd",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = virt_ssbd_needed,
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.fields = (VMStateField[]){
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VMSTATE_UINT64(env.virt_ssbd, X86CPU),
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VMSTATE_END_OF_LIST()
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}
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};
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VMStateDescription vmstate_x86_cpu = {
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VMStateDescription vmstate_x86_cpu = {
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.name = "cpu",
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.name = "cpu",
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.version_id = 12,
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.version_id = 12,
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@ -1015,6 +1034,7 @@ VMStateDescription vmstate_x86_cpu = {
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&vmstate_spec_ctrl,
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&vmstate_spec_ctrl,
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&vmstate_mcg_ext_ctl,
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&vmstate_mcg_ext_ctl,
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&vmstate_msr_intel_pt,
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&vmstate_msr_intel_pt,
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&vmstate_msr_virt_ssbd,
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NULL
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NULL
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}
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}
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};
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};
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