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target/arm: Convert T16 adjust sp (immediate)

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-56-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2019-09-04 12:30:45 -07:00 committed by Peter Maydell
parent 90aa042115
commit 2e6a646d7b
2 changed files with 11 additions and 13 deletions
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9
target/arm/t16.decode
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@ -156,6 +156,15 @@ ADD_rrri 0100 0100 . .... ... @addsub_2h s=0
CMP_xrri 0100 0101 . .... ... @addsub_2h s=1
MOV_rxri 0100 0110 . .... ... @addsub_2h s=0
# Adjust SP (immediate)
%imm7_0x4 0:7 !function=times_4
@addsub_sp_i .... .... . ....... \
&s_rri_rot s=0 rd=13 rn=13 rot=0 imm=%imm7_0x4
ADD_rri 1011 0000 0 ....... @addsub_sp_i
SUB_rri 1011 0000 1 ....... @addsub_sp_i
# Branch and exchange
@branchr .... .... . rm:4 ... &r

15
target/arm/translate.c
View file

@ -10765,19 +10765,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
/* misc */
op = (insn >> 8) & 0xf;
switch (op) {
case 0:
/*
* 0b1011_0000_xxxx_xxxx
* - ADD (SP plus immediate)
* - SUB (SP minus immediate)
*/
tmp = load_reg(s, 13);
val = (insn & 0x7f) * 4;
if (insn & (1 << 7))
val = -(int32_t)val;
tcg_gen_addi_i32(tmp, tmp, val);
store_sp_checked(s, tmp);
break;
case 0: /* add/sub (sp, immediate), in decodetree */
goto illegal_op;
case 2: /* sign/zero extend. */
ARCH(6);