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i8239: Introduce per-PIC output interrupt
As a first step towards more generic master-slave support, remove parent_irq in favor of a per-PIC output interrupt line. The slave's line is attached to IRQ2 of the master, but it remains unused for now. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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parent
620260174a
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2e2b227499
1 changed files with 12 additions and 9 deletions
21
hw/i8259.c
21
hw/i8259.c
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@ -58,6 +58,7 @@ typedef struct PicState {
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uint8_t single_mode; /* true if slave pic is not initialized */
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uint8_t elcr; /* PIIX edge/trigger selection*/
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uint8_t elcr_mask;
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qemu_irq int_out;
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PicState2 *pics_state;
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MemoryRegion base_io;
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MemoryRegion elcr_io;
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@ -67,7 +68,6 @@ struct PicState2 {
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/* 0 is master pic, 1 is slave pic */
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/* XXX: better separation between the two pics */
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PicState pics[2];
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qemu_irq parent_irq;
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void *irq_request_opaque;
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};
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@ -148,9 +148,9 @@ static void pic_update_irq(PicState2 *s)
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}
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printf("pic: cpu_interrupt\n");
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#endif
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qemu_irq_raise(s->parent_irq);
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qemu_irq_raise(s->pics[0].int_out);
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} else {
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qemu_irq_lower(s->parent_irq);
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qemu_irq_lower(s->pics[0].int_out);
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}
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}
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@ -297,7 +297,7 @@ static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
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/* init */
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pic_reset(s);
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/* deassert a pending interrupt */
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qemu_irq_lower(s->pics_state->parent_irq);
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qemu_irq_lower(s->pics_state->pics[0].int_out);
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s->init_state = 1;
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s->init4 = val & 1;
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s->single_mode = val & 2;
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@ -502,8 +502,10 @@ static const MemoryRegionOps pic_elcr_ioport_ops = {
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};
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/* XXX: add generic master/slave system */
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static void pic_init1(int io_addr, int elcr_addr, PicState *s)
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static void pic_init(int io_addr, int elcr_addr, PicState *s, qemu_irq int_out)
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{
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s->int_out = int_out;
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memory_region_init_io(&s->base_io, &pic_base_ioport_ops, s, "pic", 2);
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memory_region_init_io(&s->elcr_io, &pic_elcr_ioport_ops, s, "elcr", 1);
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@ -553,16 +555,17 @@ void irq_info(Monitor *mon)
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qemu_irq *i8259_init(qemu_irq parent_irq)
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{
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qemu_irq *irqs;
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PicState2 *s;
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s = g_malloc0(sizeof(PicState2));
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pic_init1(0x20, 0x4d0, &s->pics[0]);
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pic_init1(0xa0, 0x4d1, &s->pics[1]);
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irqs = qemu_allocate_irqs(i8259_set_irq, s, 16);
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pic_init(0x20, 0x4d0, &s->pics[0], parent_irq);
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pic_init(0xa0, 0x4d1, &s->pics[1], irqs[2]);
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s->pics[0].elcr_mask = 0xf8;
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s->pics[1].elcr_mask = 0xde;
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s->parent_irq = parent_irq;
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s->pics[0].pics_state = s;
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s->pics[1].pics_state = s;
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isa_pic = s;
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return qemu_allocate_irqs(i8259_set_irq, s, 16);
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return irqs;
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}
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