system/qemu
system/qemu
1
0
Fork 0
mirror of https://gitlab.com/qemu-project/qemu synced 2024-11-05 20:35:44 +00:00
Code Issues Projects Releases Packages Wiki Activity

hw/i386/pc: Store pointers to IDE buses in PCMachineState

Browse source 
Add the two IDE bus BusState pointers to the set we keep in PCMachineState.
This allows us to avoid passing them to pc_cmos_init(), and also will
allow a refactoring of how we call pc_cmos_init_late().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[PMD: Do not zero-init pcms->idebus[] again]
Message-ID: <20240220160622.114437-2-peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Peter Maydell 2024-02-20 16:06:13 +00:00 committed by Philippe Mathieu-Daudé
parent 16bd024bb4
commit 2df87da190
4 changed files with 12 additions and 18 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
hw/i386/pc.c
View file

@ -574,7 +574,6 @@ static void pc_cmos_init_late(void *opaque)
}
void pc_cmos_init(PCMachineState *pcms,
BusState *idebus0, BusState *idebus1,
ISADevice *rtc)
{
int val;
@ -634,8 +633,8 @@ void pc_cmos_init(PCMachineState *pcms,
/* hard drives and FDC */
arg.rtc_state = s;
arg.idebus[0] = idebus0;
arg.idebus[1] = idebus1;
arg.idebus[0] = pcms->idebus[0];
arg.idebus[1] = pcms->idebus[1];
qemu_register_reset(pc_cmos_init_late, &arg);
}

12
hw/i386/pc_piix.c
View file

@ -68,7 +68,6 @@
#include "kvm/kvm-cpu.h"
#include "target/i386/cpu.h"
#define MAX_IDE_BUS 2
#define XEN_IOAPIC_NUM_PIRQS 128ULL
#ifdef CONFIG_IDE_ISA
@ -114,7 +113,6 @@ static void pc_init1(MachineState *machine,
Object *piix4_pm = NULL;
qemu_irq smi_irq;
GSIState *gsi_state;
BusState *idebus[MAX_IDE_BUS];
ISADevice *rtc_state;
MemoryRegion *ram_memory;
MemoryRegion *pci_memory = NULL;
@ -299,8 +297,8 @@ static void pc_init1(MachineState *machine,
piix4_pm = object_resolve_path_component(OBJECT(pci_dev), "pm");
dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide"));
pci_ide_create_devs(PCI_DEVICE(dev));
idebus[0] = qdev_get_child_bus(dev, "ide.0");
idebus[1] = qdev_get_child_bus(dev, "ide.1");
pcms->idebus[0] = qdev_get_child_bus(dev, "ide.0");
pcms->idebus[1] = qdev_get_child_bus(dev, "ide.1");
} else {
isa_bus = isa_bus_new(NULL, system_memory, system_io,
&error_abort);
@ -312,8 +310,6 @@ static void pc_init1(MachineState *machine,
i8257_dma_init(OBJECT(machine), isa_bus, 0);
pcms->hpet_enabled = false;
idebus[0] = NULL;
idebus[1] = NULL;
}
if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) {
@ -358,12 +354,12 @@ static void pc_init1(MachineState *machine,
* second one.
*/
busname[4] = '0' + i;
idebus[i] = qdev_get_child_bus(DEVICE(dev), busname);
pcms->idebus[i] = qdev_get_child_bus(DEVICE(dev), busname);
}
}
#endif
pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
pc_cmos_init(pcms, rtc_state);
if (piix4_pm) {
smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0);

9
hw/i386/pc_q35.c
View file

@ -126,7 +126,6 @@ static void pc_q35_init(MachineState *machine)
PCIBus *host_bus;
PCIDevice *lpc;
DeviceState *lpc_dev;
BusState *idebus[MAX_SATA_PORTS];
ISADevice *rtc_state;
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *system_io = get_system_io();
@ -300,13 +299,11 @@ static void pc_q35_init(MachineState *machine)
ICH9_SATA1_FUNC),
"ich9-ahci");
ich9 = ICH9_AHCI(pdev);
idebus[0] = qdev_get_child_bus(DEVICE(pdev), "ide.0");
idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1");
pcms->idebus[0] = qdev_get_child_bus(DEVICE(pdev), "ide.0");
pcms->idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1");
g_assert(MAX_SATA_PORTS == ich9->ahci.ports);
ide_drive_get(hd, ich9->ahci.ports);
ahci_ide_create_devs(&ich9->ahci, hd);
} else {
idebus[0] = idebus[1] = NULL;
}
if (machine_usb(machine)) {
@ -327,7 +324,7 @@ static void pc_q35_init(MachineState *machine)
smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
}
pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
pc_cmos_init(pcms, rtc_state);
/* the rest devices to which pci devfn is automatically assigned */
pc_vga_init(isa_bus, host_bus);

4
include/hw/i386/pc.h
View file

@ -17,6 +17,8 @@
#define HPET_INTCAP "hpet-intcap"
#define MAX_IDE_BUS 2
/**
* PCMachineState:
* @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
@ -37,6 +39,7 @@ typedef struct PCMachineState {
PFlashCFI01 *flash[2];
ISADevice *pcspk;
DeviceState *iommu;
BusState *idebus[MAX_IDE_BUS];
/* Configuration options: */
uint64_t max_ram_below_4g;
@ -182,7 +185,6 @@ void pc_basic_device_init(struct PCMachineState *pcms,
bool create_fdctrl,
uint32_t hpet_irqs);
void pc_cmos_init(PCMachineState *pcms,
BusState *ide0, BusState *ide1,
ISADevice *s);
void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus);