mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-09-06 09:55:55 +00:00
tcg/mips: Fix type of tcg_target_reg_alloc_order[]
The MIPS TCG backend is the only one to have tcg_target_reg_alloc_order[] elements of type TCGReg rather than int. This resulted in commit91478cefaa
("tcg: Allocate indirect_base temporaries in a different order") breaking the build on MIPS since the type differed from indirect_reg_alloc_order[]: tcg/tcg.c:1725:44: error: pointer type mismatch in conditional expression [-Werror] order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order; ^ Make it an array of ints to fix the build and match other architectures. Fixes:91478cefaa
("tcg: Allocate indirect_base temporaries in a different order") Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <1459522179-6584-1-git-send-email-james.hogan@imgtec.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
parent
43b0ea1a41
commit
2dc7553d0c
|
@ -76,7 +76,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
|
|||
#define TCG_TMP1 TCG_REG_T9
|
||||
|
||||
/* check if we really need so many registers :P */
|
||||
static const TCGReg tcg_target_reg_alloc_order[] = {
|
||||
static const int tcg_target_reg_alloc_order[] = {
|
||||
/* Call saved registers. */
|
||||
TCG_REG_S0,
|
||||
TCG_REG_S1,
|
||||
|
|
Loading…
Reference in a new issue