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Hexagon: fix outdated hex_new_*
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Some code comments refer to hex_new_value and hex_new_pred_value, which have been transferred to DisasContext and, in the case of hex_new_value, should now be accessed through get_result_gpr(). In order to fix this outdated comments and also avoid having to tweak them whenever we make a variable name change in the future, let's replace them with pseudocode. Suggested-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <8e1689e28dd7b1318369b55127cf47b82ab75921.1684939078.git.quic_mathbern@quicinc.com>
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@ -878,9 +878,9 @@ static void gen_endloop0(DisasContext *ctx)
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*/
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if (!ctx->is_tight_loop) {
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/*
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* if (hex_gpr[HEX_REG_LC0] > 1) {
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* PC = hex_gpr[HEX_REG_SA0];
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* hex_new_value[HEX_REG_LC0] = hex_gpr[HEX_REG_LC0] - 1;
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* if (LC0 > 1) {
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* PC = SA0;
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* LC0--;
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* }
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*/
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TCGLabel *label3 = gen_new_label();
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@ -897,9 +897,9 @@ static void gen_endloop0(DisasContext *ctx)
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static void gen_endloop1(DisasContext *ctx)
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{
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/*
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* if (hex_gpr[HEX_REG_LC1] > 1) {
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* PC = hex_gpr[HEX_REG_SA1];
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* hex_new_value[HEX_REG_LC1] = hex_gpr[HEX_REG_LC1] - 1;
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* if (LC1 > 1) {
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* PC = SA1;
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* LC1--;
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* }
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*/
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TCGLabel *label = gen_new_label();
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@ -946,14 +946,12 @@ static void gen_endloop01(DisasContext *ctx)
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gen_set_label(label2);
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/*
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* if (hex_gpr[HEX_REG_LC0] > 1) {
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* PC = hex_gpr[HEX_REG_SA0];
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* hex_new_value[HEX_REG_LC0] = hex_gpr[HEX_REG_LC0] - 1;
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* } else {
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* if (hex_gpr[HEX_REG_LC1] > 1) {
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* hex_next_pc = hex_gpr[HEX_REG_SA1];
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* hex_new_value[HEX_REG_LC1] = hex_gpr[HEX_REG_LC1] - 1;
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* }
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* if (LC0 > 1) {
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* PC = SA0;
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* LC0--;
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* } else if (LC1 > 1) {
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* PC = SA1;
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* LC1--;
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* }
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*/
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tcg_gen_brcondi_tl(TCG_COND_LEU, hex_gpr[HEX_REG_LC0], 1, label3);
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@ -556,7 +556,7 @@ static void gen_start_packet(DisasContext *ctx)
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}
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/*
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* Preload the predicated pred registers into hex_new_pred_value[pred_num]
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* Preload the predicated pred registers into ctx->new_pred_value[pred_num]
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* Only endloop instructions conditionally write to pred registers
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*/
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if (ctx->need_commit && pkt->pkt_has_endloop) {
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