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tests/tcg/tricore: Uses label for memory addresses

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the linker might rearrange sections, so lets reference memory by label
name instead of addr + off.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230526061946.54514-3-kbastian@mail.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2023-05-26 08:19:42 +02:00
parent 8b50d564be
commit 2b8e2992c3
3 changed files with 6 additions and 7 deletions
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1
tests/tcg/tricore/asm/macros.h
View file

@ -25,7 +25,6 @@
#define AREG_ADDR %a0
#define AREG_CORRECT_RESULT %a3
#define MEM_BASE_ADDR 0xd0000000
#define DREG_DEV_ADDR %a15

4
tests/tcg/tricore/asm/test_ld_bu.S
View file

@ -9,7 +9,7 @@ _start:
# expect. addr reg val after load
# insn num expect. load value | pattern for loading
# | | | | |
TEST_LD(ld.bu, 1, 0xff, MEM_BASE_ADDR + 4, [+AREG_ADDR]4) # pre_inc
TEST_LD(ld.bu, 2, 0xad, MEM_BASE_ADDR + 4, [AREG_ADDR+]4) # post_inc
TEST_LD(ld.bu, 1, 0xff, test_data + 4, [+AREG_ADDR]4) # pre_inc
TEST_LD(ld.bu, 2, 0xad, test_data + 4, [AREG_ADDR+]4) # post_inc
TEST_PASSFAIL

8
tests/tcg/tricore/asm/test_ld_h.S
View file

@ -7,9 +7,9 @@ test_data:
.global _start
_start:
# expect. addr reg val after load
# insn num expect. load value | pattern for loading
# | | | | |
TEST_LD (ld.h, 1, 0xffffaffe, MEM_BASE_ADDR, [AREG_ADDR]2)
TEST_LD_SRO(ld.h, 2, 0x000022ff, MEM_BASE_ADDR, [AREG_ADDR]4)
# insn num expect. load value | pattern for loading
# | | | | |
TEST_LD (ld.h, 1, 0xffffaffe, test_data, [AREG_ADDR]2)
TEST_LD_SRO(ld.h, 2, 0x000022ff, test_data, [AREG_ADDR]4)
TEST_PASSFAIL