mirror of
https://gitlab.com/qemu-project/qemu
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Improve PIE and other linkage
Fix for decodetree vs Python3 floor division operator Fix i386 INDEX_op_dup2_vec expansion Fix loongson multimedia condition instructions -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAl6CvfcdHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+XrggApayNTkf5iPVa3UT7 6iMlA0rKjzck7PUf4vxSnkiHKhBQ95Lkck9U2kSTjO4utzFEV/iirYL9HhbNfZgH J9HsfSPnE2I/AzT8hKWK0UMLXK8/lroTAPmMPZcUt7usL6VVj5aH8UDBKYKALsGd We3eSPdmdTxbAvmLE2Axa55R+YHJihrBaaY0BoDBSmQCqufy554HQmVKkJzbn5pw BQFKkKbdGillgptteUmT6lDlBOJ4Vs4DicPrxXV6ERfYGuLmfwC/zHvcWQj+3wV7 FPlQN55qmcUy0Wqo4CIys3nQqF6ken4anpu+wGm4cC9YOuh6YGdUrJ7zr0rtyN1y f/3J5g== =muAX -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200330' into staging Improve PIE and other linkage Fix for decodetree vs Python3 floor division operator Fix i386 INDEX_op_dup2_vec expansion Fix loongson multimedia condition instructions # gpg: Signature made Tue 31 Mar 2020 04:50:15 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20200330: decodetree: Use Python3 floor division operator tcg/i386: Fix INDEX_op_dup2_vec target/mips: Fix loongson multimedia condition instructions configure: Support -static-pie if requested configure: Override the os default with --disable-pie configure: Unnest detection of -z,relro and -z,now configure: Always detect -no-pie toolchain support configure: Do not force pie=no for non-x86 tcg: Remove softmmu code_gen_buffer fixed address configure: Drop adjustment of textseg Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
2a95551e8b
6 changed files with 78 additions and 126 deletions
2
Makefile
2
Makefile
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@ -795,7 +795,7 @@ rm -f $(MANUAL_BUILDDIR)/$1/objects.inv $(MANUAL_BUILDDIR)/$1/searchindex.js $(M
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endef
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distclean: clean
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rm -f config-host.mak config-host.h* config-host.ld $(DOCS)
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rm -f config-host.mak config-host.h* $(DOCS)
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rm -f tests/tcg/config-*.mak
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rm -f config-all-devices.mak config-all-disas.mak config.status
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rm -f $(SUBDIR_DEVICES_MAK)
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@ -1043,47 +1043,20 @@ static inline void *alloc_code_gen_buffer(void)
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{
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int prot = PROT_WRITE | PROT_READ | PROT_EXEC;
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int flags = MAP_PRIVATE | MAP_ANONYMOUS;
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uintptr_t start = 0;
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size_t size = tcg_ctx->code_gen_buffer_size;
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void *buf;
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/* Constrain the position of the buffer based on the host cpu.
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Note that these addresses are chosen in concert with the
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addresses assigned in the relevant linker script file. */
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# if defined(__PIE__) || defined(__PIC__)
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/* Don't bother setting a preferred location if we're building
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a position-independent executable. We're more likely to get
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an address near the main executable if we let the kernel
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choose the address. */
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# elif defined(__x86_64__) && defined(MAP_32BIT)
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/* Force the memory down into low memory with the executable.
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Leave the choice of exact location with the kernel. */
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flags |= MAP_32BIT;
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/* Cannot expect to map more than 800MB in low memory. */
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if (size > 800u * 1024 * 1024) {
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tcg_ctx->code_gen_buffer_size = size = 800u * 1024 * 1024;
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}
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# elif defined(__sparc__)
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start = 0x40000000ul;
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# elif defined(__s390x__)
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start = 0x90000000ul;
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# elif defined(__mips__)
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# if _MIPS_SIM == _ABI64
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start = 0x128000000ul;
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# else
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start = 0x08000000ul;
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# endif
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# endif
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buf = mmap((void *)start, size, prot, flags, -1, 0);
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buf = mmap(NULL, size, prot, flags, -1, 0);
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if (buf == MAP_FAILED) {
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return NULL;
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}
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#ifdef __mips__
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if (cross_256mb(buf, size)) {
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/* Try again, with the original still mapped, to avoid re-acquiring
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that 256mb crossing. This time don't specify an address. */
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/*
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* Try again, with the original still mapped, to avoid re-acquiring
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* the same 256mb crossing.
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*/
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size_t size2;
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void *buf2 = mmap(NULL, size, prot, flags, -1, 0);
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switch ((int)(buf2 != MAP_FAILED)) {
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116
configure
vendored
116
configure
vendored
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@ -1067,7 +1067,6 @@ for opt do
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;;
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--static)
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static="yes"
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QEMU_LDFLAGS="-static $QEMU_LDFLAGS"
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QEMU_PKG_CONFIG_FLAGS="--static $QEMU_PKG_CONFIG_FLAGS"
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;;
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--mandir=*) mandir="$optarg"
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@ -2089,11 +2088,6 @@ if test "$static" = "yes" ; then
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if test "$modules" = "yes" ; then
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error_exit "static and modules are mutually incompatible"
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fi
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if test "$pie" = "yes" ; then
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error_exit "static and pie are mutually incompatible"
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else
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pie="no"
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fi
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fi
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# Unconditional check for compiler __thread support
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@ -2107,51 +2101,52 @@ if ! compile_prog "-Werror" "" ; then
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"Thread-Local Storage (TLS). Please upgrade to a version that does."
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fi
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if test "$pie" = ""; then
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case "$cpu-$targetos" in
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i386-Linux|x86_64-Linux|x32-Linux|i386-OpenBSD|x86_64-OpenBSD)
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;;
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*)
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pie="no"
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;;
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esac
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fi
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if test "$pie" != "no" ; then
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cat > $TMPC << EOF
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cat > $TMPC << EOF
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#ifdef __linux__
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# define THREAD __thread
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#else
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# define THREAD
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#endif
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static THREAD int tls_var;
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int main(void) { return tls_var; }
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EOF
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# check we support --no-pie first...
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if compile_prog "-Werror -fno-pie" "-no-pie"; then
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CFLAGS_NOPIE="-fno-pie"
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LDFLAGS_NOPIE="-nopie"
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fi
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if compile_prog "-fPIE -DPIE" "-pie"; then
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# Check we support --no-pie first; we will need this for building ROMs.
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if compile_prog "-Werror -fno-pie" "-no-pie"; then
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CFLAGS_NOPIE="-fno-pie"
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LDFLAGS_NOPIE="-no-pie"
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fi
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if test "$static" = "yes"; then
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if test "$pie" != "no" && compile_prog "-fPIE -DPIE" "-static-pie"; then
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QEMU_CFLAGS="-fPIE -DPIE $QEMU_CFLAGS"
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QEMU_LDFLAGS="-pie $QEMU_LDFLAGS"
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QEMU_LDFLAGS="-static-pie $QEMU_LDFLAGS"
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pie="yes"
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if compile_prog "" "-Wl,-z,relro -Wl,-z,now" ; then
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QEMU_LDFLAGS="-Wl,-z,relro -Wl,-z,now $QEMU_LDFLAGS"
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fi
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elif test "$pie" = "yes"; then
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error_exit "-static-pie not available due to missing toolchain support"
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else
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if test "$pie" = "yes"; then
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error_exit "PIE not available due to missing toolchain support"
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else
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echo "Disabling PIE due to missing toolchain support"
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pie="no"
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fi
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QEMU_LDFLAGS="-static $QEMU_LDFLAGS"
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pie="no"
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fi
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elif test "$pie" = "no"; then
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QEMU_CFLAGS="$CFLAGS_NOPIE $QEMU_CFLAGS"
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QEMU_LDFLAGS="$LDFLAGS_NOPIE $QEMU_LDFLAGS"
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elif compile_prog "-fPIE -DPIE" "-pie"; then
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QEMU_CFLAGS="-fPIE -DPIE $QEMU_CFLAGS"
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QEMU_LDFLAGS="-pie $QEMU_LDFLAGS"
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pie="yes"
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elif test "$pie" = "yes"; then
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error_exit "PIE not available due to missing toolchain support"
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else
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echo "Disabling PIE due to missing toolchain support"
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pie="no"
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fi
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# Detect support for PT_GNU_RELRO + DT_BIND_NOW.
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# The combination is known as "full relro", because .got.plt is read-only too.
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if compile_prog "" "-Wl,-z,relro -Wl,-z,now" ; then
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QEMU_LDFLAGS="-Wl,-z,relro -Wl,-z,now $QEMU_LDFLAGS"
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fi
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##########################################
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@ -6498,49 +6493,6 @@ if test "$cpu" = "s390x" ; then
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fi
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fi
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# Probe for the need for relocating the user-only binary.
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if ( [ "$linux_user" = yes ] || [ "$bsd_user" = yes ] ) && [ "$pie" = no ]; then
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textseg_addr=
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case "$cpu" in
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arm | i386 | ppc* | s390* | sparc* | x86_64 | x32)
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# ??? Rationale for choosing this address
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textseg_addr=0x60000000
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;;
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mips)
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# A 256M aligned address, high in the address space, with enough
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# room for the code_gen_buffer above it before the stack.
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textseg_addr=0x60000000
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;;
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esac
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if [ -n "$textseg_addr" ]; then
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cat > $TMPC <<EOF
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int main(void) { return 0; }
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EOF
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textseg_ldflags="-Wl,-Ttext-segment=$textseg_addr"
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if ! compile_prog "" "$textseg_ldflags"; then
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# In case ld does not support -Ttext-segment, edit the default linker
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# script via sed to set the .text start addr. This is needed on FreeBSD
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# at least.
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if ! $ld --verbose >/dev/null 2>&1; then
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error_exit \
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"We need to link the QEMU user mode binaries at a" \
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"specific text address. Unfortunately your linker" \
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"doesn't support either the -Ttext-segment option or" \
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"printing the default linker script with --verbose." \
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"If you don't want the user mode binaries, pass the" \
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"--disable-user option to configure."
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fi
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$ld --verbose | sed \
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-e '1,/==================================================/d' \
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-e '/==================================================/,$d' \
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-e "s/[.] = [0-9a-fx]* [+] SIZEOF_HEADERS/. = $textseg_addr + SIZEOF_HEADERS/" \
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-e "s/__executable_start = [0-9a-fx]*/__executable_start = $textseg_addr/" > config-host.ld
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textseg_ldflags="-Wl,-T../config-host.ld"
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fi
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fi
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fi
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# Check that the C++ compiler exists and works with the C compiler.
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# All the QEMU_CXXFLAGS are based on QEMU_CFLAGS. Keep this at the end to don't miss any other that could be added.
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if has $cxx; then
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@ -8175,10 +8127,6 @@ if test "$gprof" = "yes" ; then
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fi
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fi
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if test "$target_linux_user" = "yes" || test "$target_bsd_user" = "yes" ; then
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ldflags="$ldflags $textseg_ldflags"
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fi
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# Newer kernels on s390 check for an S390_PGSTE program header and
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# enable the pgste page table extensions in that case. This makes
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# the vm.allocate_pgste sysctl unnecessary. We enable this program
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@ -1025,7 +1025,7 @@ def output_code(self, i, extracted, outerbits, outermask):
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if extracted < self.width:
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output(ind, 'insn = ', decode_function,
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'_load_bytes(ctx, insn, {0}, {1});\n'
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.format(extracted / 8, self.width / 8));
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.format(extracted // 8, self.width // 8));
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extracted = self.width
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# Attempt to aid the compiler in producing compact switch statements.
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@ -1079,7 +1079,7 @@ def output_code(self, i, extracted, outerbits, outermask):
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if extracted < self.width:
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output(ind, 'insn = ', decode_function,
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'_load_bytes(ctx, insn, {0}, {1});\n'
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.format(extracted / 8, self.width / 8));
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.format(extracted // 8, self.width // 8));
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extracted = self.width
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output(ind, 'return insn;\n')
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# end SizeLeaf
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@ -5529,6 +5529,7 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
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{
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uint32_t opc, shift_max;
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TCGv_i64 t0, t1;
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TCGCond cond;
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opc = MASK_LMI(ctx->opcode);
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switch (opc) {
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@ -5862,14 +5863,39 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
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case OPC_SEQU_CP2:
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case OPC_SEQ_CP2:
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cond = TCG_COND_EQ;
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goto do_cc_cond;
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break;
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case OPC_SLTU_CP2:
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cond = TCG_COND_LTU;
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goto do_cc_cond;
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break;
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case OPC_SLT_CP2:
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cond = TCG_COND_LT;
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goto do_cc_cond;
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break;
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case OPC_SLEU_CP2:
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cond = TCG_COND_LEU;
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goto do_cc_cond;
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break;
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case OPC_SLE_CP2:
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/*
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* ??? Document is unclear: Set FCC[CC]. Does that mean the
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* FD field is the CC field?
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*/
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cond = TCG_COND_LE;
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do_cc_cond:
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{
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int cc = (ctx->opcode >> 8) & 0x7;
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TCGv_i64 t64 = tcg_temp_new_i64();
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TCGv_i32 t32 = tcg_temp_new_i32();
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tcg_gen_setcond_i64(cond, t64, t0, t1);
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tcg_gen_extrl_i64_i32(t32, t64);
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tcg_gen_deposit_i32(fpu_fcr31, fpu_fcr31, t32,
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get_fp_bit(cc), 1);
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tcg_temp_free_i32(t32);
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tcg_temp_free_i64(t64);
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}
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goto no_rd;
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break;
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default:
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MIPS_INVAL("loongson_cp2");
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generate_exception_end(ctx, EXCP_RI);
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@ -5878,6 +5904,7 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
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gen_store_fpr64(ctx, t0, rd);
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no_rd:
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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}
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@ -2855,9 +2855,13 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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goto gen_simd;
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#if TCG_TARGET_REG_BITS == 32
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case INDEX_op_dup2_vec:
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/* Constraints have already placed both 32-bit inputs in xmm regs. */
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insn = OPC_PUNPCKLDQ;
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goto gen_simd;
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/* First merge the two 32-bit inputs to a single 64-bit element. */
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tcg_out_vex_modrm(s, OPC_PUNPCKLDQ, a0, a1, a2);
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/* Then replicate the 64-bit elements across the rest of the vector. */
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if (type != TCG_TYPE_V64) {
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tcg_out_dup_vec(s, type, MO_64, a0, a0);
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}
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break;
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#endif
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case INDEX_op_abs_vec:
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insn = abs_insn[vece];
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|
|
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