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acpi/cxl: Add _OSC implementation (9.14.2)
CXL 2.0 specification adds 2 new dwords to the existing _OSC definition
from PCIe. The new dwords are accessed with a new uuid. This
implementation supports what is in the specification.
iasl -d decodes the result of this patch as:
Name (SUPP, Zero)
Name (CTRL, Zero)
Name (SUPC, Zero)
Name (CTRC, Zero)
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
CreateDWordField (Arg3, Zero, CDW1)
If (((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */) || (Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc") /* Unknown UUID */)))
{
CreateDWordField (Arg3, 0x04, CDW2)
CreateDWordField (Arg3, 0x08, CDW3)
Local0 = CDW3 /* \_SB_.PC0C._OSC.CDW3 */
Local0 &= 0x1F
If ((Arg1 != One))
{
CDW1 |= 0x08
}
If ((CDW3 != Local0))
{
CDW1 |= 0x10
}
SUPP = CDW2 /* \_SB_.PC0C._OSC.CDW2 */
CTRL = CDW3 /* \_SB_.PC0C._OSC.CDW3 */
CDW3 = Local0
If ((Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc") /* Unknown UUID */))
{
CreateDWordField (Arg3, 0x0C, CDW4)
CreateDWordField (Arg3, 0x10, CDW5)
SUPC = CDW4 /* \_SB_.PC0C._OSC.CDW4 */
CTRC = CDW5 /* \_SB_.PC0C._OSC.CDW5 */
CDW5 |= One
}
Return (Arg3)
}
Else
{
CDW1 |= 0x04
Return (Arg3)
}
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-25-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Ben Widawsky
Michael S. Tsirkin
parent
6e4e3ae936
commit
2a3282c68e
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@ -5,6 +5,7 @@ config ACPI_X86
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bool
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select ACPI
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select ACPI_NVDIMM
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select ACPI_CXL
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select ACPI_CPU_HOTPLUG
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select ACPI_MEMORY_HOTPLUG
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select ACPI_HMAT
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@ -66,3 +67,7 @@ config ACPI_ERST
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bool
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default y
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depends on ACPI && PCI
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config ACPI_CXL
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bool
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depends on ACPI
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12
hw/acpi/cxl-stub.c
Normal file
12
hw/acpi/cxl-stub.c
Normal file
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@ -0,0 +1,12 @@
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/*
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* Stubs for ACPI platforms that don't support CXl
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*/
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#include "qemu/osdep.h"
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#include "hw/acpi/aml-build.h"
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#include "hw/acpi/cxl.h"
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void build_cxl_osc_method(Aml *dev)
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{
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g_assert_not_reached();
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}
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130
hw/acpi/cxl.c
Normal file
130
hw/acpi/cxl.c
Normal file
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@ -0,0 +1,130 @@
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/*
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* CXL ACPI Implementation
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*
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* Copyright(C) 2020 Intel Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "qemu/osdep.h"
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#include "hw/cxl/cxl.h"
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#include "hw/acpi/acpi.h"
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#include "hw/acpi/aml-build.h"
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#include "hw/acpi/bios-linker-loader.h"
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#include "hw/acpi/cxl.h"
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#include "qapi/error.h"
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#include "qemu/uuid.h"
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static Aml *__build_cxl_osc_method(void)
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{
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Aml *method, *if_uuid, *else_uuid, *if_arg1_not_1, *if_cxl, *if_caps_masked;
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Aml *a_ctrl = aml_local(0);
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Aml *a_cdw1 = aml_name("CDW1");
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method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
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/* CDW1 is used for the return value so is present whether or not a match occurs */
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aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
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/*
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* Generate shared section between:
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* CXL 2.0 - 9.14.2.1.4 and
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* PCI Firmware Specification 3.0
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* 4.5.1. _OSC Interface for PCI Host Bridge Devices
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* The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
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* identified by the Universal Unique IDentifier (UUID)
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* 33DB4D5B-1FF7-401C-9657-7441C03DD766
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* The _OSC interface for a CXL Host bridge is
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* identified by the UUID 68F2D50B-C469-4D8A-BD3D-941A103FD3FC
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* A CXL Host bridge is compatible with a PCI host bridge so
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* for the shared section match both.
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*/
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if_uuid = aml_if(
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aml_lor(aml_equal(aml_arg(0),
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aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")),
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aml_equal(aml_arg(0),
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aml_touuid("68F2D50B-C469-4D8A-BD3D-941A103FD3FC"))));
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aml_append(if_uuid, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
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aml_append(if_uuid, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
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aml_append(if_uuid, aml_store(aml_name("CDW3"), a_ctrl));
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/*
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*
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* Allows OS control for all 5 features:
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* PCIeHotplug SHPCHotplug PME AER PCIeCapability
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*/
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aml_append(if_uuid, aml_and(a_ctrl, aml_int(0x1F), a_ctrl));
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/*
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* Check _OSC revision.
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* PCI Firmware specification 3.3 and CXL 2.0 both use revision 1
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* Unknown Revision is CDW1 - BIT (3)
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*/
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if_arg1_not_1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
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aml_append(if_arg1_not_1, aml_or(a_cdw1, aml_int(0x08), a_cdw1));
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aml_append(if_uuid, if_arg1_not_1);
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if_caps_masked = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
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/* Capability bits were masked */
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aml_append(if_caps_masked, aml_or(a_cdw1, aml_int(0x10), a_cdw1));
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aml_append(if_uuid, if_caps_masked);
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aml_append(if_uuid, aml_store(aml_name("CDW2"), aml_name("SUPP")));
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aml_append(if_uuid, aml_store(aml_name("CDW3"), aml_name("CTRL")));
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/* Update DWORD3 (the return value) */
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aml_append(if_uuid, aml_store(a_ctrl, aml_name("CDW3")));
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/* CXL only section as per CXL 2.0 - 9.14.2.1.4 */
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if_cxl = aml_if(aml_equal(
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aml_arg(0), aml_touuid("68F2D50B-C469-4D8A-BD3D-941A103FD3FC")));
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/* CXL support field */
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aml_append(if_cxl, aml_create_dword_field(aml_arg(3), aml_int(12), "CDW4"));
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/* CXL capabilities */
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aml_append(if_cxl, aml_create_dword_field(aml_arg(3), aml_int(16), "CDW5"));
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aml_append(if_cxl, aml_store(aml_name("CDW4"), aml_name("SUPC")));
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aml_append(if_cxl, aml_store(aml_name("CDW5"), aml_name("CTRC")));
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/* CXL 2.0 Port/Device Register access */
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aml_append(if_cxl,
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aml_or(aml_name("CDW5"), aml_int(0x1), aml_name("CDW5")));
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aml_append(if_uuid, if_cxl);
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aml_append(if_uuid, aml_return(aml_arg(3)));
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aml_append(method, if_uuid);
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/*
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* If no UUID matched, return Unrecognized UUID via Arg3 DWord 1
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* ACPI 6.4 - 6.2.11
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* Unrecognised UUID - BIT(2)
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*/
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else_uuid = aml_else();
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aml_append(else_uuid,
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aml_or(aml_name("CDW1"), aml_int(0x4), aml_name("CDW1")));
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aml_append(else_uuid, aml_return(aml_arg(3)));
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aml_append(method, else_uuid);
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return method;
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}
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void build_cxl_osc_method(Aml *dev)
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{
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aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
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aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
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aml_append(dev, aml_name_decl("SUPC", aml_int(0)));
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aml_append(dev, aml_name_decl("CTRC", aml_int(0)));
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aml_append(dev, __build_cxl_osc_method());
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}
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@ -13,6 +13,7 @@ acpi_ss.add(when: 'CONFIG_ACPI_MEMORY_HOTPLUG', if_false: files('acpi-mem-hotplu
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acpi_ss.add(when: 'CONFIG_ACPI_NVDIMM', if_true: files('nvdimm.c'))
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acpi_ss.add(when: 'CONFIG_ACPI_NVDIMM', if_false: files('acpi-nvdimm-stub.c'))
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acpi_ss.add(when: 'CONFIG_ACPI_PCI', if_true: files('pci.c'))
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acpi_ss.add(when: 'CONFIG_ACPI_CXL', if_true: files('cxl.c'), if_false: files('cxl-stub.c'))
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acpi_ss.add(when: 'CONFIG_ACPI_VMGENID', if_true: files('vmgenid.c'))
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acpi_ss.add(when: 'CONFIG_ACPI_HW_REDUCED', if_true: files('generic_event_device.c'))
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acpi_ss.add(when: 'CONFIG_ACPI_HMAT', if_true: files('hmat.c'))
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@ -33,4 +34,5 @@ softmmu_ss.add_all(when: 'CONFIG_ACPI', if_true: acpi_ss)
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softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('acpi-stub.c', 'aml-build-stub.c',
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'acpi-x86-stub.c', 'ipmi-stub.c', 'ghes-stub.c',
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'acpi-mem-hotplug-stub.c', 'acpi-cpu-hotplug-stub.c',
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'acpi-pci-hotplug-stub.c', 'acpi-nvdimm-stub.c'))
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'acpi-pci-hotplug-stub.c', 'acpi-nvdimm-stub.c',
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'cxl-stub.c'))
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@ -67,6 +67,7 @@
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#include "hw/acpi/aml-build.h"
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#include "hw/acpi/utils.h"
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#include "hw/acpi/pci.h"
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#include "hw/acpi/cxl.h"
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#include "qom/qom-qobject.h"
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#include "hw/i386/amd_iommu.h"
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@ -1582,11 +1583,15 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
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aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
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aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
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if (pci_bus_is_cxl(bus)) {
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aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
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aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
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struct Aml *pkg = aml_package(2);
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/* Expander bridges do not have ACPI PCI Hot-plug enabled */
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aml_append(dev, build_q35_osc_method(true));
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aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016")));
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aml_append(pkg, aml_eisaid("PNP0A08"));
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aml_append(pkg, aml_eisaid("PNP0A03"));
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aml_append(dev, aml_name_decl("_CID", pkg));
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aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
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aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
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build_cxl_osc_method(dev);
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} else if (pci_bus_is_express(bus)) {
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aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
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aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
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23
include/hw/acpi/cxl.h
Normal file
23
include/hw/acpi/cxl.h
Normal file
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@ -0,0 +1,23 @@
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/*
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* Copyright (C) 2020 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_ACPI_CXL_H
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#define HW_ACPI_CXL_H
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void build_cxl_osc_method(Aml *dev);
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#endif
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