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Realview/EB procid hacks

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Guess core tile ID based on CPU type.

Signed-off-by: Paul Brook <paul@codesourcery.com>
This commit is contained in:
Paul Brook 2009-11-13 03:30:33 +00:00
parent dbe73d7f3b
commit 26e92f6552
4 changed files with 18 additions and 6 deletions
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8
hw/arm_sysctl.c
View file

@ -25,6 +25,7 @@ typedef struct {
uint32_t flags;
uint32_t nvflags;
uint32_t resetlevel;
uint32_t proc_id;
} arm_sysctl_state;
static void arm_sysctl_reset(DeviceState *d)
@ -89,8 +90,7 @@ static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
case 0x60: /* MISC */
return 0;
case 0x84: /* PROCID0 */
/* ??? Don't know what the proper value for the core tile ID is. */
return 0x02000000;
return s->proc_id;
case 0x88: /* PROCID1 */
return 0xff000000;
case 0x64: /* DMAPSR0 */
@ -215,13 +215,14 @@ static int arm_sysctl_init1(SysBusDevice *dev)
}
/* Legacy helper function. */
void arm_sysctl_init(uint32_t base, uint32_t sys_id)
void arm_sysctl_init(uint32_t base, uint32_t sys_id, uint32_t proc_id)
{
DeviceState *dev;
dev = qdev_create(NULL, "realview_sysctl");
qdev_prop_set_uint32(dev, "sys_id", sys_id);
qdev_init_nofail(dev);
qdev_prop_set_uint32(dev, "proc_id", proc_id);
sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
}
@ -232,6 +233,7 @@ static SysBusDeviceInfo arm_sysctl_info = {
.qdev.reset = arm_sysctl_reset,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
DEFINE_PROP_END_OF_LIST(),
}
};

2
hw/primecell.h
View file

@ -9,6 +9,6 @@
void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
/* arm_sysctl.c */
void arm_sysctl_init(uint32_t base, uint32_t sys_id);
void arm_sysctl_init(uint32_t base, uint32_t sys_id, uint32_t proc_id);
#endif

12
hw/realview.c
View file

@ -51,6 +51,7 @@ static void realview_init(ram_addr_t ram_size,
int done_smc = 0;
qemu_irq cpu_irq[4];
int ncpu;
uint32_t proc_id = 0;
if (!cpu_model)
cpu_model = "arm926";
@ -73,13 +74,22 @@ static void realview_init(ram_addr_t ram_size,
qemu_register_reset(secondary_cpu_reset, env);
}
}
if (arm_feature(env, ARM_FEATURE_V7)) {
proc_id = 0x0e000000;
} else if (arm_feature(env, ARM_FEATURE_V6K)) {
proc_id = 0x06000000;
} else if (arm_feature(env, ARM_FEATURE_V6)) {
proc_id = 0x04000000;
} else {
proc_id = 0x02000000;
}
ram_offset = qemu_ram_alloc(ram_size);
/* ??? RAM should repeat to fill physical memory space. */
/* SDRAM at address zero. */
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
arm_sysctl_init(0x10000000, 0xc1400400);
arm_sysctl_init(0x10000000, 0xc1400400, proc_id);
if (ncpu == 1) {
/* ??? The documentation says GIC1 is nFIQ and either GIC2 or GIC3

2
hw/versatilepb.c
View file

@ -184,7 +184,7 @@ static void versatile_init(ram_addr_t ram_size,
/* SDRAM at address zero. */
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
arm_sysctl_init(0x10000000, 0x41007004);
arm_sysctl_init(0x10000000, 0x41007004, 0x02000000);
cpu_pic = arm_pic_init_cpu(env);
dev = sysbus_create_varargs("pl190", 0x10140000,
cpu_pic[0], cpu_pic[1], NULL);