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target/arm: Use TRANS_FEAT for FMMLA
Being able to specify the feature predicate in TRANS_FEAT makes it easier to split trans_FMMLA by element size, which also happens to simplify the decode. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220527181907.189259-79-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -1598,10 +1598,9 @@ SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx
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USDOT_zzzz 01000100 .. 0 ..... 011 110 ..... ..... @rda_rn_rm
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### SVE2 floating point matrix multiply accumulate
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{
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BFMMLA 01100100 01 1 ..... 111 001 ..... ..... @rda_rn_rm_e0
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FMMLA 01100100 .. 1 ..... 111 001 ..... ..... @rda_rn_rm
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}
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BFMMLA 01100100 01 1 ..... 111 001 ..... ..... @rda_rn_rm_e0
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FMMLA_s 01100100 10 1 ..... 111 001 ..... ..... @rda_rn_rm_e0
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FMMLA_d 01100100 11 1 ..... 111 001 ..... ..... @rda_rn_rm_e0
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### SVE2 Memory Gather Load Group
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@ -7318,29 +7318,10 @@ DO_SVE2_ZPZZ_FP(FMINP, fminp)
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* SVE Integer Multiply-Add (unpredicated)
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*/
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static bool trans_FMMLA(DisasContext *s, arg_rrrr_esz *a)
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{
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gen_helper_gvec_4_ptr *fn;
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switch (a->esz) {
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case MO_32:
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if (!dc_isar_feature(aa64_sve_f32mm, s)) {
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return false;
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}
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fn = gen_helper_fmmla_s;
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break;
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case MO_64:
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if (!dc_isar_feature(aa64_sve_f64mm, s)) {
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return false;
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}
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fn = gen_helper_fmmla_d;
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break;
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default:
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return false;
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}
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return gen_gvec_fpst_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR);
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}
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TRANS_FEAT(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_s,
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a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR)
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TRANS_FEAT(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_d,
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a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR)
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static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] = {
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NULL, gen_helper_sve2_sqdmlal_zzzw_h,
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