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hw/char/pl011: better handling of FIFO flags on LCR reset
Current FIFO handling code does not reset RXFE/RXFF flags when guest resets FIFO by writing to UARTLCR register, although internal FIFO state is reset to 0 read count. Actual guest-visible flag update will happen only on next data read or write attempt. As a result of that any guest that expects RXFE flag to be set (and RXFF to be cleared) after resetting FIFO will never see that happen. Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230123162304.26254-5-eiakovlev@linux.microsoft.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -92,6 +92,16 @@ static inline unsigned pl011_get_fifo_depth(PL011State *s)
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return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1;
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}
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static inline void pl011_reset_fifo(PL011State *s)
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{
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s->read_count = 0;
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s->read_pos = 0;
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/* Reset FIFO flags */
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s->flags &= ~(PL011_FLAG_RXFF | PL011_FLAG_TXFF);
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s->flags |= PL011_FLAG_RXFE | PL011_FLAG_TXFE;
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}
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static uint64_t pl011_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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@ -239,8 +249,7 @@ static void pl011_write(void *opaque, hwaddr offset,
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case 11: /* UARTLCR_H */
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/* Reset the FIFO state on FIFO enable or disable */
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if ((s->lcr ^ value) & 0x10) {
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s->read_count = 0;
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s->read_pos = 0;
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pl011_reset_fifo(s);
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}
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if ((s->lcr ^ value) & 0x1) {
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int break_enable = value & 0x1;
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@ -450,12 +459,11 @@ static void pl011_reset(DeviceState *dev)
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s->ilpr = 0;
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s->ibrd = 0;
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s->fbrd = 0;
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s->read_pos = 0;
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s->read_count = 0;
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s->read_trigger = 1;
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s->ifl = 0x12;
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s->cr = 0x300;
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s->flags = 0x90;
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s->flags = 0;
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pl011_reset_fifo(s);
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}
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static void pl011_class_init(ObjectClass *oc, void *data)
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