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target/riscv: csr: Remove redundant check in fp csr read/write routines
The following check: if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -RISCV_EXCP_ILLEGAL_INST; } is redundant in fflags/frm/fcsr read/write routines, as the check was already done in fs(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210627120604.11116-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -215,11 +215,6 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
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static RISCVException read_fflags(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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#if !defined(CONFIG_USER_ONLY)
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if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
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return RISCV_EXCP_ILLEGAL_INST;
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}
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#endif
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*val = riscv_cpu_get_fflags(env);
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return RISCV_EXCP_NONE;
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}
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@ -228,9 +223,6 @@ static RISCVException write_fflags(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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#if !defined(CONFIG_USER_ONLY)
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if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
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return RISCV_EXCP_ILLEGAL_INST;
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}
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env->mstatus |= MSTATUS_FS;
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#endif
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riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
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@ -240,11 +232,6 @@ static RISCVException write_fflags(CPURISCVState *env, int csrno,
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static RISCVException read_frm(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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#if !defined(CONFIG_USER_ONLY)
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if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
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return RISCV_EXCP_ILLEGAL_INST;
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}
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#endif
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*val = env->frm;
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return RISCV_EXCP_NONE;
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}
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@ -253,9 +240,6 @@ static RISCVException write_frm(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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#if !defined(CONFIG_USER_ONLY)
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if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
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return RISCV_EXCP_ILLEGAL_INST;
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}
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env->mstatus |= MSTATUS_FS;
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#endif
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env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
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@ -265,11 +249,6 @@ static RISCVException write_frm(CPURISCVState *env, int csrno,
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static RISCVException read_fcsr(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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#if !defined(CONFIG_USER_ONLY)
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if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
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return RISCV_EXCP_ILLEGAL_INST;
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}
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#endif
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*val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
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| (env->frm << FSR_RD_SHIFT);
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if (vs(env, csrno) >= 0) {
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@ -283,9 +262,6 @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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#if !defined(CONFIG_USER_ONLY)
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if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
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return RISCV_EXCP_ILLEGAL_INST;
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}
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env->mstatus |= MSTATUS_FS;
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#endif
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env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
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