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Fix dynamic tlb resize
Fix x86 host vector saturation Diagnose missing tcg labels -----BEGIN PGP SIGNATURE----- iQEcBAABAgAGBQJcYamQAAoJEGTfOOivfiFfNb4H/3DiEHDTfai7VJTuSvYWeS2M gS2UEpHoSTgqf/QFEv2OdHRynm3lzrOaYluiKnN67EThbvqKAz2dDfqjh1FuEs6i YnWnvFvZlw6ABoCgZugXdmCVVzn4OrOy2Pdu/YjKVaLwwfRbjWgDVDlJpnIBagsi ItAGvbEyAXUAxXTDP+hvmGS4V6MwQBzMyLhzaoUOTaF9lmb2JDMteYYxCWCP9gfS ApISkm8/+OulBR26DA4gPt6C4URk+7M3QeVf9ApANTkgrk9ikrTiShs5QxgO3hme +MzCP/vjvSLzbQt67eQ1JXVYiKs3ZSGY6o+mzIThmd4zKQWveys1QEPgGQ1l+jU= =yJ4z -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190211' into staging Fix dynamic tlb resize Fix x86 host vector saturation Diagnose missing tcg labels # gpg: Signature made Mon 11 Feb 2019 16:57:52 GMT # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20190211: cputlb: update TLB entry/index after tlb_fill exec-all: document that tlb_fill can trigger a TLB resize tcg/i386: fix unsigned vector saturating arithmetic tcg: Diagnose referenced labels that have not been emitted Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
22c5f44651
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@ -1045,6 +1045,8 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr)
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if (unlikely(!tlb_hit(entry->addr_code, addr))) {
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if (!VICTIM_TLB_HIT(addr_code, addr)) {
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tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0);
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index = tlb_index(env, mmu_idx, addr);
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entry = tlb_entry(env, mmu_idx, addr);
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}
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assert(tlb_hit(entry->addr_code, addr));
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}
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@ -1125,6 +1127,8 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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if (!VICTIM_TLB_HIT(addr_write, addr)) {
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tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_STORE,
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mmu_idx, retaddr);
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index = tlb_index(env, mmu_idx, addr);
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tlbe = tlb_entry(env, mmu_idx, addr);
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}
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tlb_addr = tlb_addr_write(tlbe) & ~TLB_INVALID_MASK;
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}
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@ -129,6 +129,8 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr,
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if (!VICTIM_TLB_HIT(ADDR_READ, addr)) {
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tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE,
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mmu_idx, retaddr);
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index = tlb_index(env, mmu_idx, addr);
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entry = tlb_entry(env, mmu_idx, addr);
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}
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tlb_addr = entry->ADDR_READ;
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}
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@ -198,6 +200,8 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr,
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if (!VICTIM_TLB_HIT(ADDR_READ, addr)) {
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tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE,
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mmu_idx, retaddr);
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index = tlb_index(env, mmu_idx, addr);
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entry = tlb_entry(env, mmu_idx, addr);
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}
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tlb_addr = entry->ADDR_READ;
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}
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@ -294,6 +298,8 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
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if (!VICTIM_TLB_HIT(addr_write, addr)) {
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tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE,
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mmu_idx, retaddr);
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index = tlb_index(env, mmu_idx, addr);
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entry = tlb_entry(env, mmu_idx, addr);
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}
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tlb_addr = tlb_addr_write(entry) & ~TLB_INVALID_MASK;
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}
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@ -372,6 +378,8 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
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if (!VICTIM_TLB_HIT(addr_write, addr)) {
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tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE,
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mmu_idx, retaddr);
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index = tlb_index(env, mmu_idx, addr);
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entry = tlb_entry(env, mmu_idx, addr);
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}
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tlb_addr = tlb_addr_write(entry) & ~TLB_INVALID_MASK;
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}
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@ -475,6 +475,11 @@ static inline void assert_no_pages_locked(void)
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struct MemoryRegionSection *iotlb_to_section(CPUState *cpu,
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hwaddr index, MemTxAttrs attrs);
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/*
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* Note: tlb_fill() can trigger a resize of the TLB. This means that all of the
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* caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must
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* be discarded and looked up again (e.g. via tlb_entry()).
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*/
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void tlb_fill(CPUState *cpu, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);
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@ -2615,7 +2615,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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OPC_PADDSB, OPC_PADDSW, OPC_UD2, OPC_UD2
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};
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static int const usadd_insn[4] = {
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OPC_PADDSB, OPC_PADDSW, OPC_UD2, OPC_UD2
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OPC_PADDUB, OPC_PADDUW, OPC_UD2, OPC_UD2
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};
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static int const sub_insn[4] = {
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OPC_PSUBB, OPC_PSUBW, OPC_PSUBD, OPC_PSUBQ
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@ -2624,7 +2624,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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OPC_PSUBSB, OPC_PSUBSW, OPC_UD2, OPC_UD2
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};
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static int const ussub_insn[4] = {
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OPC_PSUBSB, OPC_PSUBSW, OPC_UD2, OPC_UD2
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OPC_PSUBUB, OPC_PSUBUW, OPC_UD2, OPC_UD2
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};
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static int const mul_insn[4] = {
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OPC_UD2, OPC_PMULLW, OPC_PMULLD, OPC_UD2
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@ -255,6 +255,7 @@ static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
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static inline void gen_set_label(TCGLabel *l)
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{
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l->present = 1;
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tcg_gen_op1(INDEX_op_set_label, label_arg(l));
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}
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23
tcg/tcg.c
23
tcg/tcg.c
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@ -305,6 +305,9 @@ TCGLabel *gen_new_label(void)
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*l = (TCGLabel){
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.id = s->nb_labels++
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};
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#ifdef CONFIG_DEBUG_TCG
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QSIMPLEQ_INSERT_TAIL(&s->labels, l, next);
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#endif
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return l;
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}
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@ -1092,6 +1095,9 @@ void tcg_func_start(TCGContext *s)
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QTAILQ_INIT(&s->ops);
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QTAILQ_INIT(&s->free_ops);
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#ifdef CONFIG_DEBUG_TCG
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QSIMPLEQ_INIT(&s->labels);
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#endif
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}
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static inline TCGTemp *tcg_temp_alloc(TCGContext *s)
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@ -3841,6 +3847,23 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
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}
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#endif
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#ifdef CONFIG_DEBUG_TCG
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/* Ensure all labels referenced have been emitted. */
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{
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TCGLabel *l;
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bool error = false;
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QSIMPLEQ_FOREACH(l, &s->labels, next) {
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if (unlikely(!l->present) && l->refs) {
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qemu_log_mask(CPU_LOG_TB_OP,
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"$L%d referenced but not present.\n", l->id);
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error = true;
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}
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}
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assert(!error);
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}
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#endif
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#ifdef CONFIG_PROFILER
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atomic_set(&prof->opt_time, prof->opt_time - profile_getclock());
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#endif
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12
tcg/tcg.h
12
tcg/tcg.h
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@ -244,16 +244,21 @@ typedef struct TCGRelocation {
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intptr_t addend;
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} TCGRelocation;
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typedef struct TCGLabel {
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typedef struct TCGLabel TCGLabel;
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struct TCGLabel {
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unsigned present : 1;
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unsigned has_value : 1;
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unsigned id : 15;
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unsigned id : 14;
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unsigned refs : 16;
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union {
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uintptr_t value;
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tcg_insn_unit *value_ptr;
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TCGRelocation *first_reloc;
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} u;
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} TCGLabel;
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#ifdef CONFIG_DEBUG_TCG
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QSIMPLEQ_ENTRY(TCGLabel) next;
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#endif
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};
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typedef struct TCGPool {
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struct TCGPool *next;
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@ -685,6 +690,7 @@ struct TCGContext {
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#endif
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#ifdef CONFIG_DEBUG_TCG
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QSIMPLEQ_HEAD(, TCGLabel) labels;
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int temps_in_use;
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int goto_tb_issue_mask;
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#endif
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