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Revert "target/arm: Make number of counters in PMCR follow the CPU"
This reverts commit f7fb73b8cd
.
This change turned out to be a bit half-baked, and doesn't
work with KVM, which fails with the error:
"qemu-system-aarch64: Failed to retrieve host CPU features"
because KVM does not allow accessing of the PMCR_EL0 value in
the scratch "query CPU ID registers" VM unless we have first
set the KVM_ARM_VCPU_PMU_V3 feature on the VM.
Revert the change for 6.0.
Reported-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Zenghui Yu <yuzenghui@huawei.com>
Message-id: 20210331154822.23332-1-peter.maydell@linaro.org
This commit is contained in:
parent
e7e0d52dc6
commit
21c2dd77a6
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@ -942,7 +942,6 @@ struct ARMCPU {
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uint64_t id_aa64mmfr2;
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uint64_t id_aa64dfr0;
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uint64_t id_aa64dfr1;
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uint64_t reset_pmcr_el0;
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} isar;
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uint64_t midr;
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uint32_t revidr;
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@ -141,7 +141,6 @@ static void aarch64_a57_initfn(Object *obj)
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cpu->gic_num_lrs = 4;
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cpu->gic_vpribits = 5;
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cpu->gic_vprebits = 5;
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cpu->isar.reset_pmcr_el0 = 0x41013000;
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define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
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}
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@ -195,7 +194,6 @@ static void aarch64_a53_initfn(Object *obj)
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cpu->gic_num_lrs = 4;
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cpu->gic_vpribits = 5;
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cpu->gic_vprebits = 5;
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cpu->isar.reset_pmcr_el0 = 0x41033000;
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define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
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}
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@ -247,7 +245,6 @@ static void aarch64_a72_initfn(Object *obj)
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cpu->gic_num_lrs = 4;
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cpu->gic_vpribits = 5;
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cpu->gic_vprebits = 5;
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cpu->isar.reset_pmcr_el0 = 0x41023000;
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define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
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}
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@ -301,7 +301,6 @@ static void cortex_a8_initfn(Object *obj)
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cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
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cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
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cpu->reset_auxcr = 2;
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cpu->isar.reset_pmcr_el0 = 0x41002000;
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define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
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}
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@ -374,7 +373,6 @@ static void cortex_a9_initfn(Object *obj)
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cpu->clidr = (1 << 27) | (1 << 24) | 3;
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cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
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cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
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cpu->isar.reset_pmcr_el0 = 0x41093000;
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define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
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}
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@ -445,7 +443,6 @@ static void cortex_a7_initfn(Object *obj)
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cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
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cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
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cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
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cpu->isar.reset_pmcr_el0 = 0x41072000;
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define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
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}
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@ -488,7 +485,6 @@ static void cortex_a15_initfn(Object *obj)
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cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
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cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
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cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
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cpu->isar.reset_pmcr_el0 = 0x410F3000;
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define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
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}
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@ -721,7 +717,6 @@ static void cortex_r5_initfn(Object *obj)
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cpu->isar.id_isar6 = 0x0;
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cpu->mp_is_up = true;
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cpu->pmsav7_dregion = 16;
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cpu->isar.reset_pmcr_el0 = 0x41151800;
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define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
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}
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@ -38,6 +38,7 @@
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#endif
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#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
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#define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */
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#ifndef CONFIG_USER_ONLY
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@ -1148,9 +1149,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
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static inline uint32_t pmu_num_counters(CPUARMState *env)
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{
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ARMCPU *cpu = env_archcpu(env);
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return (cpu->isar.reset_pmcr_el0 & PMCRN_MASK) >> PMCRN_SHIFT;
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return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
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}
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/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
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@ -5754,6 +5753,13 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
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.resetvalue = 0,
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.writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
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#endif
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/* The only field of MDCR_EL2 that has a defined architectural reset value
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* is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
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*/
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{ .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
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.access = PL2_RW, .resetvalue = PMCR_NUM_COUNTERS,
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.fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
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{ .name = "HPFAR", .state = ARM_CP_STATE_AA32,
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.cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
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.access = PL2_RW, .accessfn = access_el3_aa32ns,
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@ -6683,7 +6689,7 @@ static void define_pmu_regs(ARMCPU *cpu)
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* field as main ID register, and we implement four counters in
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* addition to the cycle count register.
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*/
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unsigned int i, pmcrn = pmu_num_counters(&cpu->env);
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unsigned int i, pmcrn = PMCR_NUM_COUNTERS;
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ARMCPRegInfo pmcr = {
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.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
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.access = PL0_RW,
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@ -6698,10 +6704,10 @@ static void define_pmu_regs(ARMCPU *cpu)
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.access = PL0_RW, .accessfn = pmreg_access,
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.type = ARM_CP_IO,
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
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.resetvalue = cpu->isar.reset_pmcr_el0,
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.resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) |
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PMCRLC,
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.writefn = pmcr_write, .raw_writefn = raw_write,
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};
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define_one_arm_cp_reg(cpu, &pmcr);
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define_one_arm_cp_reg(cpu, &pmcr64);
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for (i = 0; i < pmcrn; i++) {
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@ -7819,17 +7825,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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.fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
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REGINFO_SENTINEL
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};
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/*
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* The only field of MDCR_EL2 that has a defined architectural reset
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* value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
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*/
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ARMCPRegInfo mdcr_el2 = {
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.name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
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.access = PL2_RW, .resetvalue = pmu_num_counters(env),
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.fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2),
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};
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define_one_arm_cp_reg(cpu, &mdcr_el2);
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define_arm_cp_regs(cpu, vpidr_regs);
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define_arm_cp_regs(cpu, el2_cp_reginfo);
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if (arm_feature(env, ARM_FEATURE_V8)) {
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@ -566,8 +566,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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ARM64_SYS_REG(3, 0, 0, 7, 1));
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2,
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ARM64_SYS_REG(3, 0, 0, 7, 2));
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
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ARM64_SYS_REG(3, 3, 9, 12, 0));
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/*
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* Note that if AArch32 support is not present in the host,
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