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target/ppc: Remove fpscr_* macros from cpu.h
fpscr_* defined macros are hiding the usage of *env behind them. Substitute the usage of these macros with `env->fpscr & FP_*` to make the code cleaner. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20220504210541.115256-2-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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@ -88,7 +88,7 @@ static inline void fpscr_set_rounding_mode(CPUPPCState *env)
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int rnd_type;
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/* Set rounding mode */
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switch (fpscr_rn) {
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switch (env->fpscr & FP_RN) {
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case 0:
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/* Best approximation (round to nearest) */
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rnd_type = float_round_nearest_even;
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@ -713,41 +713,12 @@ enum {
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#define FPSCR_NI 2 /* Floating-point non-IEEE mode */
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#define FPSCR_RN1 1
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#define FPSCR_RN0 0 /* Floating-point rounding control */
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#define fpscr_drn (((env->fpscr) & FP_DRN) >> FPSCR_DRN0)
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#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
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#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
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#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
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#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
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#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
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#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
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#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
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#define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
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#define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
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#define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
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#define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
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#define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
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#define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
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#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
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#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
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#define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
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#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
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#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
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#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
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#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
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#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
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#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
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#define fpscr_rn (((env->fpscr) >> FPSCR_RN0) & 0x3)
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/* Invalid operation exception summary */
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#define FPSCR_IX ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
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(1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
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(1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
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(1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
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(1 << FPSCR_VXCVI))
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/* exception summary */
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#define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
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/* enabled exception summary */
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#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
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0x1F)
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#define FP_DRN2 (1ull << FPSCR_DRN2)
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#define FP_DRN1 (1ull << FPSCR_DRN1)
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@ -202,7 +202,7 @@ static void finish_invalid_op_excp(CPUPPCState *env, int op, uintptr_t retaddr)
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env->fpscr |= FP_VX;
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/* Update the floating-point exception summary */
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env->fpscr |= FP_FX;
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if (fpscr_ve != 0) {
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if (env->fpscr & FP_VE) {
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/* Update the floating-point enabled exception summary */
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env->fpscr |= FP_FEX;
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if (fp_exceptions_enabled(env)) {
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@ -216,7 +216,7 @@ static void finish_invalid_op_arith(CPUPPCState *env, int op,
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bool set_fpcc, uintptr_t retaddr)
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{
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env->fpscr &= ~(FP_FR | FP_FI);
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if (fpscr_ve == 0) {
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if (!(env->fpscr & FP_VE)) {
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if (set_fpcc) {
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env->fpscr &= ~FP_FPCC;
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env->fpscr |= (FP_C | FP_FU);
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@ -286,7 +286,7 @@ static void float_invalid_op_vxvc(CPUPPCState *env, bool set_fpcc,
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/* Update the floating-point exception summary */
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env->fpscr |= FP_FX;
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/* We must update the target FPR before raising the exception */
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if (fpscr_ve != 0) {
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if (env->fpscr & FP_VE) {
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CPUState *cs = env_cpu(env);
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cs->exception_index = POWERPC_EXCP_PROGRAM;
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@ -303,7 +303,7 @@ static void float_invalid_op_vxcvi(CPUPPCState *env, bool set_fpcc,
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{
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env->fpscr |= FP_VXCVI;
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env->fpscr &= ~(FP_FR | FP_FI);
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if (fpscr_ve == 0) {
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if (!(env->fpscr & FP_VE)) {
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if (set_fpcc) {
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env->fpscr &= ~FP_FPCC;
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env->fpscr |= (FP_C | FP_FU);
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@ -318,7 +318,7 @@ static inline void float_zero_divide_excp(CPUPPCState *env, uintptr_t raddr)
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env->fpscr &= ~(FP_FR | FP_FI);
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/* Update the floating-point exception summary */
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env->fpscr |= FP_FX;
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if (fpscr_ze != 0) {
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if (env->fpscr & FP_ZE) {
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/* Update the floating-point enabled exception summary */
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env->fpscr |= FP_FEX;
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if (fp_exceptions_enabled(env)) {
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@ -336,7 +336,7 @@ static inline void float_overflow_excp(CPUPPCState *env)
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env->fpscr |= FP_OX;
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/* Update the floating-point exception summary */
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env->fpscr |= FP_FX;
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if (fpscr_oe != 0) {
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if (env->fpscr & FP_OE) {
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/* XXX: should adjust the result */
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/* Update the floating-point enabled exception summary */
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env->fpscr |= FP_FEX;
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@ -356,7 +356,7 @@ static inline void float_underflow_excp(CPUPPCState *env)
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env->fpscr |= FP_UX;
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/* Update the floating-point exception summary */
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env->fpscr |= FP_FX;
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if (fpscr_ue != 0) {
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if (env->fpscr & FP_UE) {
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/* XXX: should adjust the result */
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/* Update the floating-point enabled exception summary */
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env->fpscr |= FP_FEX;
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@ -374,7 +374,7 @@ static inline void float_inexact_excp(CPUPPCState *env)
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env->fpscr |= FP_XX;
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/* Update the floating-point exception summary */
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env->fpscr |= FP_FX;
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if (fpscr_xe != 0) {
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if (env->fpscr & FP_XE) {
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/* Update the floating-point enabled exception summary */
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env->fpscr |= FP_FEX;
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/* We must update the target FPR before raising the exception */
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@ -2274,7 +2274,7 @@ VSX_MADDQ(XSNMSUBQPO, NMSUB_FLGS, 0)
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vxvc = svxvc; \
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if (flags & float_flag_invalid_snan) { \
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float_invalid_op_vxsnan(env, GETPC()); \
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vxvc &= fpscr_ve == 0; \
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vxvc &= !(env->fpscr & FP_VE); \
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} \
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if (vxvc) { \
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float_invalid_op_vxvc(env, 0, GETPC()); \
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@ -2375,7 +2375,7 @@ static inline void do_scalar_cmp(CPUPPCState *env, ppc_vsr_t *xa, ppc_vsr_t *xb,
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if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) ||
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float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) {
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vxsnan_flag = true;
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if (fpscr_ve == 0 && ordered) {
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if (!(env->fpscr & FP_VE) && ordered) {
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vxvc_flag = true;
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}
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} else if (float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) ||
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@ -2440,7 +2440,7 @@ static inline void do_scalar_cmpq(CPUPPCState *env, ppc_vsr_t *xa,
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if (float128_is_signaling_nan(xa->f128, &env->fp_status) ||
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float128_is_signaling_nan(xb->f128, &env->fp_status)) {
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vxsnan_flag = true;
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if (fpscr_ve == 0 && ordered) {
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if (!(env->fpscr & FP_VE) && ordered) {
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vxvc_flag = true;
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}
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} else if (float128_is_quiet_nan(xa->f128, &env->fp_status) ||
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@ -2590,7 +2590,7 @@ void helper_##name(CPUPPCState *env, \
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t.VsrD(0) = xb->VsrD(0); \
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} \
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\
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vex_flag = fpscr_ve & vxsnan_flag; \
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vex_flag = (env->fpscr & FP_VE) && vxsnan_flag; \
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if (vxsnan_flag) { \
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float_invalid_op_vxsnan(env, GETPC()); \
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} \
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@ -3320,7 +3320,7 @@ void helper_xsrqpi(CPUPPCState *env, uint32_t opcode,
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if (r == 0 && rmc == 0) {
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rmode = float_round_ties_away;
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} else if (r == 0 && rmc == 0x3) {
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rmode = fpscr_rn;
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rmode = env->fpscr & FP_RN;
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} else if (r == 1) {
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switch (rmc) {
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case 0:
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@ -3374,7 +3374,7 @@ void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode,
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if (r == 0 && rmc == 0) {
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rmode = float_round_ties_away;
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} else if (r == 0 && rmc == 0x3) {
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rmode = fpscr_rn;
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rmode = env->fpscr & FP_RN;
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} else if (r == 1) {
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switch (rmc) {
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case 0:
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