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target/mips: Fix if-else-switch-case arms checkpatch errors in translate.c
Remove if-else-switch-case-arms-related checkpatch errors. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <1561037595-14413-5-git-send-email-aleksandar.markovic@rt-rk.com>
This commit is contained in:
Aleksandar Markovic
parent
235785e834
commit
1f8929d241
1 changed files with 133 additions and 72 deletions
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@ -2619,16 +2619,18 @@ static const char * const mxuregnames[] = {
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/* General purpose registers moves. */
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static inline void gen_load_gpr(TCGv t, int reg)
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{
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if (reg == 0)
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if (reg == 0) {
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tcg_gen_movi_tl(t, 0);
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else
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} else {
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tcg_gen_mov_tl(t, cpu_gpr[reg]);
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}
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}
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static inline void gen_store_gpr(TCGv t, int reg)
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{
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if (reg != 0)
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if (reg != 0) {
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tcg_gen_mov_tl(cpu_gpr[reg], t);
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}
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}
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/* Moves to/from shadow registers. */
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@ -2636,9 +2638,9 @@ static inline void gen_load_srsgpr(int from, int to)
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{
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TCGv t0 = tcg_temp_new();
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if (from == 0)
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if (from == 0) {
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tcg_gen_movi_tl(t0, 0);
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else {
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} else {
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TCGv_i32 t2 = tcg_temp_new_i32();
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TCGv_ptr addr = tcg_temp_new_ptr();
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@ -2841,10 +2843,11 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
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static inline int get_fp_bit(int cc)
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{
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if (cc)
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if (cc) {
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return 24 + cc;
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else
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} else {
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return 23;
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}
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}
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/* Addresses computation */
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@ -2908,14 +2911,16 @@ static inline void gen_move_high32(TCGv ret, TCGv_i64 arg)
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static inline void check_cp0_enabled(DisasContext *ctx)
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{
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if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))
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if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
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generate_exception_err(ctx, EXCP_CpU, 0);
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}
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}
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static inline void check_cp1_enabled(DisasContext *ctx)
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{
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if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU)))
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if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) {
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generate_exception_err(ctx, EXCP_CpU, 1);
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}
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}
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/* Verify that the processor is running with COP1X instructions enabled.
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@ -2924,8 +2929,9 @@ static inline void check_cp1_enabled(DisasContext *ctx)
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static inline void check_cop1x(DisasContext *ctx)
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{
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if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X)))
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if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) {
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generate_exception_end(ctx, EXCP_RI);
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}
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}
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/* Verify that the processor is running with 64-bit floating-point
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@ -2933,8 +2939,9 @@ static inline void check_cop1x(DisasContext *ctx)
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static inline void check_cp1_64bitmode(DisasContext *ctx)
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{
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if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X)))
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if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) {
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generate_exception_end(ctx, EXCP_RI);
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}
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}
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/*
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@ -2950,8 +2957,9 @@ static inline void check_cp1_64bitmode(DisasContext *ctx)
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*/
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static inline void check_cp1_registers(DisasContext *ctx, int regs)
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{
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if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1)))
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if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) {
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generate_exception_end(ctx, EXCP_RI);
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}
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}
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/* Verify that the processor is running with DSP instructions enabled.
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@ -3040,8 +3048,9 @@ static inline void check_ps(DisasContext *ctx)
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instructions are not enabled. */
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static inline void check_mips_64(DisasContext *ctx)
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{
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if (unlikely(!(ctx->hflags & MIPS_HFLAG_64)))
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if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {
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generate_exception_end(ctx, EXCP_RI);
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}
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}
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#endif
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@ -3126,13 +3135,12 @@ static inline void check_nms(DisasContext *ctx)
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*/
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static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx)
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{
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if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS)) &&
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!(ctx->CP0_Config1 & (1 << CP0C1_DL)) &&
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!(ctx->CP0_Config1 & (1 << CP0C1_IL)) &&
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!(ctx->CP0_Config2 & (1 << CP0C2_SL)) &&
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!(ctx->CP0_Config2 & (1 << CP0C2_TL)) &&
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!(ctx->CP0_Config5 & (1 << CP0C5_L2C)))
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{
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if (unlikely((ctx->CP0_Config5 & (1 << CP0C5_NMS)) &&
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!(ctx->CP0_Config1 & (1 << CP0C1_DL)) &&
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!(ctx->CP0_Config1 & (1 << CP0C1_IL)) &&
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!(ctx->CP0_Config2 & (1 << CP0C2_SL)) &&
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!(ctx->CP0_Config2 & (1 << CP0C2_TL)) &&
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!(ctx->CP0_Config5 & (1 << CP0C5_L2C)))) {
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generate_exception_end(ctx, EXCP_RI);
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}
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}
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@ -3180,23 +3188,56 @@ static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \
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gen_ldcmp_fpr##bits (ctx, fp0, fs); \
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gen_ldcmp_fpr##bits (ctx, fp1, ft); \
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switch (n) { \
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case 0: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); break;\
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case 1: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); break;\
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case 2: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); break;\
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case 3: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); break;\
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case 4: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); break;\
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case 5: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); break;\
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case 6: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); break;\
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case 7: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); break;\
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case 8: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); break;\
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case 9: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); break;\
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case 10: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); break;\
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case 11: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); break;\
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case 12: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); break;\
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case 13: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); break;\
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case 14: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); break;\
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case 15: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); break;\
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default: abort(); \
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case 0: \
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gen_helper_0e2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); \
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break; \
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case 1: \
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gen_helper_0e2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); \
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break; \
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case 2: \
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gen_helper_0e2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); \
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break; \
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case 3: \
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gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); \
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break; \
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case 4: \
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gen_helper_0e2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); \
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break; \
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case 5: \
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gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); \
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break; \
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case 6: \
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gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); \
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break; \
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case 7: \
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gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); \
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break; \
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case 8: \
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gen_helper_0e2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); \
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break; \
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case 9: \
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gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); \
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break; \
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case 10: \
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gen_helper_0e2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); \
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break; \
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case 11: \
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gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); \
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break; \
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case 12: \
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gen_helper_0e2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); \
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break; \
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case 13: \
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gen_helper_0e2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); \
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break; \
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case 14: \
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gen_helper_0e2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); \
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break; \
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case 15: \
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gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); \
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break; \
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default: \
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abort(); \
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} \
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tcg_temp_free_i##bits (fp0); \
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tcg_temp_free_i##bits (fp1); \
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@ -3882,22 +3923,25 @@ static void gen_logic_imm(DisasContext *ctx, uint32_t opc,
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uimm = (uint16_t)imm;
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switch (opc) {
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case OPC_ANDI:
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if (likely(rs != 0))
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if (likely(rs != 0)) {
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tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
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else
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} else {
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tcg_gen_movi_tl(cpu_gpr[rt], 0);
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}
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break;
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case OPC_ORI:
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if (rs != 0)
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if (rs != 0) {
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tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
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else
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} else {
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tcg_gen_movi_tl(cpu_gpr[rt], uimm);
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}
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break;
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case OPC_XORI:
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if (likely(rs != 0))
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if (likely(rs != 0)) {
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tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
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else
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} else {
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tcg_gen_movi_tl(cpu_gpr[rt], uimm);
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}
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break;
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case OPC_LUI:
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if (rs != 0 && (ctx->insn_flags & ISA_MIPS32R6)) {
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@ -6060,8 +6104,9 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
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}
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out:
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if (insn_bytes == 2)
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if (insn_bytes == 2) {
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ctx->hflags |= MIPS_HFLAG_B16;
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}
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tcg_temp_free(t0);
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tcg_temp_free(t1);
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}
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@ -6708,8 +6753,9 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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{
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const char *register_name = "invalid";
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if (sel != 0)
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if (sel != 0) {
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check_insn(ctx, ISA_MIPS32);
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}
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switch (reg) {
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case CP0_REGISTER_00:
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@ -7464,8 +7510,9 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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{
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const char *register_name = "invalid";
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if (sel != 0)
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if (sel != 0) {
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check_insn(ctx, ISA_MIPS32);
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}
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if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
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gen_io_start();
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@ -8210,8 +8257,9 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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{
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const char *register_name = "invalid";
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if (sel != 0)
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if (sel != 0) {
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check_insn(ctx, ISA_MIPS64);
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}
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switch (reg) {
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case CP0_REGISTER_00:
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@ -8920,8 +8968,9 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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{
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const char *register_name = "invalid";
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if (sel != 0)
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if (sel != 0) {
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check_insn(ctx, ISA_MIPS64);
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}
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if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
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gen_io_start();
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@ -9658,12 +9707,12 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
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if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
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((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
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(env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
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(env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) {
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tcg_gen_movi_tl(t0, -1);
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else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
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(env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
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} else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
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(env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) {
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tcg_gen_movi_tl(t0, -1);
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else if (u == 0) {
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} else if (u == 0) {
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switch (rt) {
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case 1:
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switch (sel) {
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@ -9883,12 +9932,12 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
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gen_load_gpr(t0, rt);
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if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
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((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
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(env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
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(env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) {
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/* NOP */ ;
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else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
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(env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
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} else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
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(env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) {
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/* NOP */ ;
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else if (u == 0) {
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} else if (u == 0) {
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switch (rd) {
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case 1:
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switch (sel) {
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@ -10162,8 +10211,9 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
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break;
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case OPC_TLBWI:
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opn = "tlbwi";
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if (!env->tlb->helper_tlbwi)
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if (!env->tlb->helper_tlbwi) {
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goto die;
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}
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gen_helper_tlbwi(cpu_env);
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break;
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case OPC_TLBINV:
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@ -10186,20 +10236,23 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
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break;
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case OPC_TLBWR:
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opn = "tlbwr";
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if (!env->tlb->helper_tlbwr)
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if (!env->tlb->helper_tlbwr) {
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goto die;
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}
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gen_helper_tlbwr(cpu_env);
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break;
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case OPC_TLBP:
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opn = "tlbp";
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if (!env->tlb->helper_tlbp)
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if (!env->tlb->helper_tlbp) {
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goto die;
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}
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gen_helper_tlbp(cpu_env);
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break;
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case OPC_TLBR:
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opn = "tlbr";
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if (!env->tlb->helper_tlbr)
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if (!env->tlb->helper_tlbr) {
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goto die;
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}
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gen_helper_tlbr(cpu_env);
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break;
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case OPC_ERET: /* OPC_ERETNC */
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@ -10273,8 +10326,9 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
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goto out;
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}
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if (cc != 0)
|
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if (cc != 0) {
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check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
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}
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btarget = ctx->base.pc_next + 4 + offset;
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|
|
@ -10728,10 +10782,11 @@ static void gen_movci(DisasContext *ctx, int rd, int rs, int cc, int tf)
|
|||
return;
|
||||
}
|
||||
|
||||
if (tf)
|
||||
if (tf) {
|
||||
cond = TCG_COND_EQ;
|
||||
else
|
||||
} else {
|
||||
cond = TCG_COND_NE;
|
||||
}
|
||||
|
||||
l1 = gen_new_label();
|
||||
t0 = tcg_temp_new_i32();
|
||||
|
|
@ -10753,10 +10808,11 @@ static inline void gen_movcf_s(DisasContext *ctx, int fs, int fd, int cc,
|
|||
TCGv_i32 t0 = tcg_temp_new_i32();
|
||||
TCGLabel *l1 = gen_new_label();
|
||||
|
||||
if (tf)
|
||||
if (tf) {
|
||||
cond = TCG_COND_EQ;
|
||||
else
|
||||
} else {
|
||||
cond = TCG_COND_NE;
|
||||
}
|
||||
|
||||
tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
|
||||
tcg_gen_brcondi_i32(cond, t0, 0, l1);
|
||||
|
|
@ -10774,10 +10830,11 @@ static inline void gen_movcf_d(DisasContext *ctx, int fs, int fd, int cc,
|
|||
TCGv_i64 fp0;
|
||||
TCGLabel *l1 = gen_new_label();
|
||||
|
||||
if (tf)
|
||||
if (tf) {
|
||||
cond = TCG_COND_EQ;
|
||||
else
|
||||
} else {
|
||||
cond = TCG_COND_NE;
|
||||
}
|
||||
|
||||
tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
|
||||
tcg_gen_brcondi_i32(cond, t0, 0, l1);
|
||||
|
|
@ -10797,10 +10854,11 @@ static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd,
|
|||
TCGLabel *l1 = gen_new_label();
|
||||
TCGLabel *l2 = gen_new_label();
|
||||
|
||||
if (tf)
|
||||
if (tf) {
|
||||
cond = TCG_COND_EQ;
|
||||
else
|
||||
} else {
|
||||
cond = TCG_COND_NE;
|
||||
}
|
||||
|
||||
tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
|
||||
tcg_gen_brcondi_i32(cond, t0, 0, l1);
|
||||
|
|
@ -12096,8 +12154,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
|
|||
TCGLabel *l1 = gen_new_label();
|
||||
TCGv_i64 fp0;
|
||||
|
||||
if (ft != 0)
|
||||
if (ft != 0) {
|
||||
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
|
||||
}
|
||||
fp0 = tcg_temp_new_i64();
|
||||
gen_load_fpr64(ctx, fp0, fs);
|
||||
gen_store_fpr64(ctx, fp0, fd);
|
||||
|
|
@ -29991,12 +30050,14 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
|
|||
env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],
|
||||
env->hflags, env->btarget, env->bcond);
|
||||
for (i = 0; i < 32; i++) {
|
||||
if ((i & 3) == 0)
|
||||
if ((i & 3) == 0) {
|
||||
qemu_fprintf(f, "GPR%02d:", i);
|
||||
}
|
||||
qemu_fprintf(f, " %s " TARGET_FMT_lx,
|
||||
regnames[i], env->active_tc.gpr[i]);
|
||||
if ((i & 3) == 3)
|
||||
if ((i & 3) == 3) {
|
||||
qemu_fprintf(f, "\n");
|
||||
}
|
||||
}
|
||||
|
||||
qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx "\n",
|
||||
|
|
|
|||
Loading…
Reference in a new issue