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target/arm: Introduce gen_pc_plus_diff for aarch64
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20221020030641.2066807-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -140,9 +140,14 @@ static void reset_btype(DisasContext *s)
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}
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}
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}
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}
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static void gen_pc_plus_diff(DisasContext *s, TCGv_i64 dest, target_long diff)
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{
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tcg_gen_movi_i64(dest, s->pc_curr + diff);
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}
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void gen_a64_update_pc(DisasContext *s, target_long diff)
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void gen_a64_update_pc(DisasContext *s, target_long diff)
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{
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{
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tcg_gen_movi_i64(cpu_pc, s->pc_curr + diff);
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gen_pc_plus_diff(s, cpu_pc, diff);
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}
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}
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/*
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/*
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@ -1360,7 +1365,7 @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
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if (insn & (1U << 31)) {
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if (insn & (1U << 31)) {
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/* BL Branch with link */
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/* BL Branch with link */
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tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
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gen_pc_plus_diff(s, cpu_reg(s, 30), curr_insn_len(s));
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}
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}
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/* B Branch / BL Branch with link */
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/* B Branch / BL Branch with link */
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@ -2301,11 +2306,17 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
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default:
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default:
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goto do_unallocated;
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goto do_unallocated;
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}
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}
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gen_a64_set_pc(s, dst);
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/* BLR also needs to load return address */
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/* BLR also needs to load return address */
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if (opc == 1) {
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if (opc == 1) {
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tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
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TCGv_i64 lr = cpu_reg(s, 30);
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if (dst == lr) {
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TCGv_i64 tmp = new_tmp_a64(s);
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tcg_gen_mov_i64(tmp, dst);
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dst = tmp;
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}
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gen_pc_plus_diff(s, lr, curr_insn_len(s));
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}
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}
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gen_a64_set_pc(s, dst);
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break;
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break;
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case 8: /* BRAA */
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case 8: /* BRAA */
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@ -2328,11 +2339,17 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
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} else {
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} else {
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dst = cpu_reg(s, rn);
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dst = cpu_reg(s, rn);
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}
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}
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gen_a64_set_pc(s, dst);
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/* BLRAA also needs to load return address */
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/* BLRAA also needs to load return address */
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if (opc == 9) {
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if (opc == 9) {
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tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
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TCGv_i64 lr = cpu_reg(s, 30);
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if (dst == lr) {
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TCGv_i64 tmp = new_tmp_a64(s);
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tcg_gen_mov_i64(tmp, dst);
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dst = tmp;
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}
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gen_pc_plus_diff(s, lr, curr_insn_len(s));
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}
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}
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gen_a64_set_pc(s, dst);
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break;
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break;
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case 4: /* ERET */
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case 4: /* ERET */
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@ -2900,7 +2917,8 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
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tcg_rt = cpu_reg(s, rt);
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tcg_rt = cpu_reg(s, rt);
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clean_addr = tcg_constant_i64(s->pc_curr + imm);
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clean_addr = new_tmp_a64(s);
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gen_pc_plus_diff(s, clean_addr, imm);
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if (is_vector) {
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if (is_vector) {
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do_fp_ld(s, rt, clean_addr, size);
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do_fp_ld(s, rt, clean_addr, size);
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} else {
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} else {
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@ -4244,23 +4262,22 @@ static void disas_ldst(DisasContext *s, uint32_t insn)
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static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
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static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
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{
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{
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unsigned int page, rd;
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unsigned int page, rd;
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uint64_t base;
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int64_t offset;
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uint64_t offset;
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page = extract32(insn, 31, 1);
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page = extract32(insn, 31, 1);
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/* SignExtend(immhi:immlo) -> offset */
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/* SignExtend(immhi:immlo) -> offset */
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offset = sextract64(insn, 5, 19);
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offset = sextract64(insn, 5, 19);
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offset = offset << 2 | extract32(insn, 29, 2);
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offset = offset << 2 | extract32(insn, 29, 2);
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rd = extract32(insn, 0, 5);
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rd = extract32(insn, 0, 5);
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base = s->pc_curr;
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if (page) {
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if (page) {
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/* ADRP (page based) */
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/* ADRP (page based) */
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base &= ~0xfff;
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offset <<= 12;
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offset <<= 12;
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/* The page offset is ok for TARGET_TB_PCREL. */
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offset -= s->pc_curr & 0xfff;
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}
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}
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tcg_gen_movi_i64(cpu_reg(s, rd), base + offset);
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gen_pc_plus_diff(s, cpu_reg(s, rd), offset);
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}
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}
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/*
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/*
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