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target/arm: Introduce gen_pc_plus_diff for aarch64

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In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221020030641.2066807-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-10-20 13:06:39 +10:00 committed by Peter Maydell
parent bb0356170a
commit 19f6b76baa
1 changed files with 29 additions and 12 deletions
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41
target/arm/translate-a64.c
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@ -140,9 +140,14 @@ static void reset_btype(DisasContext *s)
}
}
static void gen_pc_plus_diff(DisasContext *s, TCGv_i64 dest, target_long diff)
{
tcg_gen_movi_i64(dest, s->pc_curr + diff);
}
void gen_a64_update_pc(DisasContext *s, target_long diff)
{
tcg_gen_movi_i64(cpu_pc, s->pc_curr + diff);
gen_pc_plus_diff(s, cpu_pc, diff);
}
/*
@ -1360,7 +1365,7 @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
if (insn & (1U << 31)) {
/* BL Branch with link */
tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
gen_pc_plus_diff(s, cpu_reg(s, 30), curr_insn_len(s));
}
/* B Branch / BL Branch with link */
@ -2301,11 +2306,17 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
default:
goto do_unallocated;
}
gen_a64_set_pc(s, dst);
/* BLR also needs to load return address */
if (opc == 1) {
tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
TCGv_i64 lr = cpu_reg(s, 30);
if (dst == lr) {
TCGv_i64 tmp = new_tmp_a64(s);
tcg_gen_mov_i64(tmp, dst);
dst = tmp;
}
gen_pc_plus_diff(s, lr, curr_insn_len(s));
}
gen_a64_set_pc(s, dst);
break;
case 8: /* BRAA */
@ -2328,11 +2339,17 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
} else {
dst = cpu_reg(s, rn);
}
gen_a64_set_pc(s, dst);
/* BLRAA also needs to load return address */
if (opc == 9) {
tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
TCGv_i64 lr = cpu_reg(s, 30);
if (dst == lr) {
TCGv_i64 tmp = new_tmp_a64(s);
tcg_gen_mov_i64(tmp, dst);
dst = tmp;
}
gen_pc_plus_diff(s, lr, curr_insn_len(s));
}
gen_a64_set_pc(s, dst);
break;
case 4: /* ERET */
@ -2900,7 +2917,8 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
tcg_rt = cpu_reg(s, rt);
clean_addr = tcg_constant_i64(s->pc_curr + imm);
clean_addr = new_tmp_a64(s);
gen_pc_plus_diff(s, clean_addr, imm);
if (is_vector) {
do_fp_ld(s, rt, clean_addr, size);
} else {
@ -4244,23 +4262,22 @@ static void disas_ldst(DisasContext *s, uint32_t insn)
static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
{
unsigned int page, rd;
uint64_t base;
uint64_t offset;
int64_t offset;
page = extract32(insn, 31, 1);
/* SignExtend(immhi:immlo) -> offset */
offset = sextract64(insn, 5, 19);
offset = offset << 2 | extract32(insn, 29, 2);
rd = extract32(insn, 0, 5);
base = s->pc_curr;
if (page) {
/* ADRP (page based) */
base &= ~0xfff;
offset <<= 12;
/* The page offset is ok for TARGET_TB_PCREL. */
offset -= s->pc_curr & 0xfff;
}
tcg_gen_movi_i64(cpu_reg(s, rd), base + offset);
gen_pc_plus_diff(s, cpu_reg(s, rd), offset);
}
/*